公开(公告)号：US11606031B1

公开(公告)日：2023-03-14

申请号：US17649527

申请日：2022-01-31

Applicant: QUALCOMM Incorporated

Inventor： Hector Ivan Oporta ,  Daragh MacGabhann ,  Chunping Song ,  Yi Wang ,  Ji Hoon Hyun

IPC: H02M3/158 ,  H03K19/0185 ,  H03K17/0412

Abstract: Power supply circuit having low quiescent current for a bypass mode. One example power supply circuit generally includes a transistor; a switching node coupled to a source of the transistor; a power supply rail; a capacitor having a first terminal coupled to the power supply rail and having a second terminal coupled to the switching node; a gate driver having an output coupled to a gate of the transistor, having a first power input coupled to the power supply rail, and having a second power input coupled to the switching node; logic having a first input coupled to the first terminal of the capacitor, having a second input coupled to the second terminal of the capacitor, and having a first output; and a pullup circuit having a control input coupled to a second output of the logic and having an output coupled to the gate of the transistor.

公开(公告)号：US10969816B2

公开(公告)日：2021-04-06

申请号：US16659686

申请日：2019-10-22

Applicant: QUALCOMM Incorporated

Inventor： Sameer Wadhwa ,  Yi Wang ,  Lennart Karl-Axel Mathe

IPC: G05F1/10 ,  G05F3/02 ,  G05F3/26 ,  G06F3/041 ,  G05F3/24

Abstract: In certain aspects, a bias generation circuit comprises a bias voltage generator. The bias voltage generator has a main NMOS transistor having a drain and a gate of the main NMOS transistor both coupled to a first terminal, a main resistor having a first main resistor terminal and a second main resistor terminal, wherein the first main resistor terminal couples to a source of the main NMOS transistor; and a main PMOS transistor having a source of the main PMOS transistor coupled to the second main resistor terminal and a drain and a gate of the main PMOS transistor both coupled to a second terminal, wherein the second terminal couples to a main ground. The bias generation circuit further comprises an array of sensors coupled to the first terminal and the second terminal.