公开(公告)号：US20250087611A1

公开(公告)日：2025-03-13

申请号：US18465717

申请日：2023-09-12

Applicant: QUALCOMM Incorporated

Inventor： Yujen CHEN ,  Yangyang SUN ,  Wei WANG

IPC: H01L23/00

Abstract: An integrated device comprising a die substrate; a plurality of pads; a plurality of inner solder interconnects coupled to the plurality of pads; and a plurality of pillar shell interconnects coupled to the plurality of inner solder interconnects. The plurality of inner solder interconnects are located between the plurality of pillar shell interconnects and the plurality of pads.

公开(公告)号：US20240413112A1

公开(公告)日：2024-12-12

申请号：US18330657

申请日：2023-06-07

Applicant: QUALCOMM Incorporated

Inventor： Dongming HE ,  Hung-Yuan HSU ,  Yujen CHEN

IPC: H01L23/00

Abstract: An integrated device includes a die having a contact pad and a solder cap electrically connected to the contact pad by a multi-layer interconnect pillar. The multi-layer interconnect pillar includes a base reinforcement layer, a cap reinforcement layer, and one or more solder layers disposed between the base reinforcement layer and the cap reinforcement layer.

公开(公告)号：US20230082120A1

公开(公告)日：2023-03-16

申请号：US17476373

申请日：2021-09-15

Applicant: QUALCOMM Incorporated

Inventor： Yujen CHEN ,  Hung-Yuan HSU ,  Dongming HE

IPC: H01L23/00 ,  H01L23/498

Abstract: A package comprising a substrate and an integrated device coupled to the substrate through a plurality of pillar interconnects and a plurality of solder interconnects. The plurality of pillar interconnects comprises a first pillar interconnect. The first pillar interconnect comprises a first pillar interconnect portion comprising a first width and a second pillar interconnect portion comprising a second width that is different than the first width.

公开(公告)号：US20230057439A1

公开(公告)日：2023-02-23

申请号：US17409334

申请日：2021-08-23

Applicant: QUALCOMM Incorporated

Inventor： Yujen CHEN ,  Hung-Yuan HSU ,  Dongming HE

IPC: H01L23/00

Abstract: A package comprising a substrate and an integrated device coupled to the substrate through a plurality of pillar interconnects and a plurality of solder interconnects. The plurality of pillar interconnects includes a first pillar interconnect comprising a first cavity. The plurality of solder interconnects comprises a first solder interconnect located in the first cavity of the first pillar interconnect. A planar cross section that extends through the first cavity of the first pillar interconnect may comprise an O shape. The first pillar interconnect comprises a first pillar interconnect portion comprising a first width; and a second pillar interconnect portion comprising a second width that is different than the first width.