FLIP-CHIP DEVICE
    2.
    发明申请

    公开(公告)号:US20210118834A1

    公开(公告)日:2021-04-22

    申请号:US17071432

    申请日:2020-10-15

    Abstract: Disclosed are devices, fabrication methods and design rules for flip-chip devices. Aspects include an apparatus including a flip-chip device. The flip-chip device including a die having a plurality of under bump metallizations (UBMs). A package substrate having a plurality of bond pads is also included. A plurality of solder joints coupling the die to the package substrate. The plurality of solder joints are formed from a plurality of solder bumps plated on the plurality of UBMs, where the plurality of solder bumps are directly connected to the plurality of bond pads.

    SEMICONDUCTOR DEVICE WITH MULTIPLE STACKED PASSIVE DEVICES

    公开(公告)号:US20240421128A1

    公开(公告)日:2024-12-19

    申请号:US18335532

    申请日:2023-06-15

    Abstract: Disclosed is a semiconductor device. In an aspect, a semiconductor device includes: a first-tier passive device including a substrate portion, a passive device portion, and a metallization portion disposed in a stacked configuration; and one or more second-tier passive devices disposed over the first-tier passive device. Each one of the one or more second-tier passive devices includes: a substrate portion, a passive device portion, and a metallization portion disposed in a stacked configuration; and a set of through substrate vias (TSVs) passing through a corresponding substrate portion and electrically coupled to a corresponding metallization portion. The semiconductor device comprises a passive component including the passive device portion of the first-tier passive device electrically coupled to one or more passive device portions of the one or more second-tier passive devices through the metallization portions of the first-tier passive device and the one or more second-tier passive devices.

    SIDEWALL WETTING BARRIER FOR CONDUCTIVE PILLARS

    公开(公告)号:US20220270995A1

    公开(公告)日:2022-08-25

    申请号:US17185244

    申请日:2021-02-25

    Abstract: Disclosed are examples of integrated circuit (IC) structures and techniques to fabricate IC structures. Each IC package may include a die (e.g., a flip-chip (FC) die) and one or more die interconnects to electrically couple the die to a substrate. The die interconnect may include a pillar, a wetting barrier on the pillar, and a solder cap on the wetting barrier. The wetting barrier may be wider than the pillar such that during solder reflow, solder wetting of sidewall of the pillar is minimized or prevented all together. The die interconnect may also include a low wetting layer formed on the wetting barrier, which can further mitigate solder wetting problems.

    FLIP-CHIP FLEXIBLE UNDER BUMP METALLIZATION SIZE

    公开(公告)号:US20210407939A1

    公开(公告)日:2021-12-30

    申请号:US16917295

    申请日:2020-06-30

    Abstract: Disclosed is a flip-chip device. The flip-chip device includes a die having a plurality of under bump metallizations (UBMs); and a package substrate having a plurality of bond pads. The plurality of UBMs include a first set of UBMs having a first size and a first minimum pitch and a second set of UBMs having a second size and a second minimum pitch. The first set of UBMs and the second set of UBMs are each electrically coupled to the package substrate by a bond-on-pad connection.

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