公开(公告)号：US20030108203A1

公开(公告)日：2003-06-12

申请号：US10015531

申请日：2001-12-12

Applicant: QuickSilver Technology, Inc.

Inventor： Sharad Sambhwani ,  Ghobad Heidari

IPC: H04K001/00

CPC classification number: H04B1/70752 ,  H04B1/70735 ,  H04B1/708 ,  H04B1/7083 ,  H04B1/7095

Abstract: A system for detecting and identifying the identity of a base station or cell which transmits a scrambling code is provided. According to one aspect of the system, the system is used to perform scrambling code detection of eight (8) primary cells (each scrambling code being spaced sixteen (16) chips apart) in a group. According to another aspect of the system, a single scrambling code generator is used to generate a master scrambling code. The master scrambling code is then used to create individual scrambling codes which are used in correlation with received signals to detect in parallel which one of the eight (8) possible primary cells in the group transmitted the received signals. According to yet another aspect of the system, each of the correlators maintains a corresponding segment of the master scrambling code. For every sixteen (16) chips, a new segment of the master scrambling code is introduced into one of the correlators, a segment of the master scrambling code is dropped from another correlator, and segments of the master scrambling code are sequentially shifted or propagated through the remaining correlators; and concurrent correlations are performed by the correlators using their respective corresponding segments of the master scrambling code and newly received signals.

Abstract translation: 提供了一种用于检测和识别发送扰码的基站或小区的身份的系统。 根据系统的一个方面，该系统用于执行八（8）个主小区（每个扰码分开间隔十六（16）个码片）的扰码检测）。 根据系统的另一方面，使用单个扰码发生器来产生主扰码。 然后，主扰码用于产生与接收信号相关使用的各个扰码，并行检测组中八（8）个可能的主小区中的哪一个发送接收信号。 根据系统的另一方面，每个相关器维护主扰码的相应段。 对于每十六（16）个芯片，主扰码的一个新的段被引入到一个相关器中，主扰码的一个段从另一个相关器中丢弃，主扰码的段被顺序地移位或传播通过 剩余的相关器; 并且相关器使用它们各自对应的主扰码和新接收的信号段执行并发相关。

公开(公告)号：US20040008640A1

公开(公告)日：2004-01-15

申请号：US10067496

申请日：2002-02-04

Applicant: QuickSilver Technology, Inc.

Inventor： Ghobad Heidari ,  Kuor-Hsin Chang

IPC: H04B007/216

CPC classification number: G06F15/7867 ,  H04B1/708 ,  H04B2201/70711

Abstract: A system for implementing a searcher for use with a communication device is provided. According to one aspect of the system, the searcher includes one or more computational units which are used to perform a PN sequence generation function to generate a sequence of PN codes. The searcher further includes a number of computational units which are used to correlate received signal samples with the PN codes. As each signal sample is received by the communication device, the received signal sample is correlated with a first PN sequence in a parallel manner using the computational units. The correlation results are then accumulated. As the next signal sample is received, this newly received signal sample is similarly correlated with the next PN sequence in a parallel manner. Likewise, the correlation results are accumulated with the previous correlation results. The foregoing process is repeated until all the signal samples needed for correlation are received and correlated with sequences of PN codes. According to another aspect of the system, the a computational units are implemented using adaptive hardware resources. The number of computational units which are used to implement the correlation function is adjustable depending on, for example, the amount of available adaptive hardware resources.

Abstract translation: 提供了一种用于实现与通信设备一起使用的搜索器的系统。 根据该系统的一个方面，搜索器包括一个或多个计算单元，用于执行PN序列生成功能以产生PN码序列。 搜索器还包括多个计算单元，用于将接收到的信号采样与PN码相关联。 由于每个信号采样由通信设备接收，所以接收的信号样本使用计算单元并行地与第一PN序列相关。 然后累积相关结果。 当接收到下一个信号样本时，新接收的信号样本与下一个PN序列以并行方式类似地相关。 同样地，相关结果与先前的相关结果一起累积。 重复上述过程，直到接收到相关所需的所有信号样本并与PN码的序列相关联。 根据系统的另一方面，使用自适应硬件资源来实现计算单元。 用于实现相关函数的计算单元的数量可以根据例如可用的自适应硬件资源的量来调整。

公开(公告)号：US20030227884A1

公开(公告)日：2003-12-11

申请号：US10015537

申请日：2001-12-12

Applicant: QuickSilver Technology, Inc.

Inventor： Sharad Sambhwani ,  Ghobad Heidari

IPC: H04B007/216

CPC classification number: H04B1/708 ,  H04B1/70735 ,  H04B1/7083

Abstract: A system for detecting and identifying the identity of a base station or cell which transmits a scrambling code is provided. According to one aspect of the system, the system is used to perform scrambling code detection of eight (8) primary cells (each scrambling code being spaced sixteen (16) chips apart) in a group. According to another aspect of the system, a single scrambling code generator is used to generate a master scrambling code. The master scrambling code is then used to create individual scrambling codes which are used in correlation with received signals to detect in parallel which one of the eight (8) possible primary cells in the group transmitted the received signals.

Abstract translation: 提供了一种用于检测和识别发送扰码的基站或小区的身份的系统。 根据系统的一个方面，该系统用于执行八（8）个主小区（每个扰码分开间隔十六（16）个码片）的扰码检测）。 根据系统的另一方面，使用单个扰码发生器来产生主扰码。 然后，主扰码用于产生与接收信号相关使用的各个扰码，并行检测组中八（8）个可能的主小区中的哪一个发送接收信号。

公开(公告)号：US20030123666A1

公开(公告)日：2003-07-03

申请号：US10295692

申请日：2002-11-14

Applicant: QuickSilver Technology, Inc.

Inventor： Sharad Sambhwani ,  Ghobad Heidari

IPC: H04K001/00

CPC classification number: H04B1/70735 ,  H04B1/70752 ,  H04B1/708 ,  H04B1/7083 ,  H04B1/7095

Abstract: A system for detecting and identifying the identity of a base station or cell which transmits a scrambling code is provided. According to one aspect of the system, the system is used to perform scrambling code detection of eight (8) primary cells (each scrambling code's X-component being spaced sixteen (16) chips apart) in a group. According to another aspect of the system, a single scrambling code generator is used to generate a master scrambling code. The master scrambling code is then used to create individual scrambling codes which are used in correlation with received signals to detect in parallel which one of the eight (8) possible primary cells in the group transmitted the received signals. According to yet another aspect of the system, each of the correlators maintains a corresponding X-component segment of the master scrambling code. For every sixteen (16) chips, a new X-component segment of the master scrambling code is introduced into one of the correlators, a X-component segment of the master scrambling code is dropped from another correlator, and X-component segments of the master scrambling code are sequentially shifted or propagated through the remaining correlators; and concurrent correlations are performed by the correlators using their respective corresponding X-component segments of the master scrambling code and newly received signals.

公开(公告)号：US20030108012A1

公开(公告)日：2003-06-12

申请号：US10295632

申请日：2002-11-14

Applicant: QuickSilver Technology, Inc.

Inventor： Sharad Sambhwani ,  Ghobad Heidari

IPC: H04B007/216

CPC classification number: H04B1/708 ,  H04B1/70735 ,  H04B1/7083

Abstract: A system for detecting and identifying the identity of a base station or cell which transmits a scrambling code is provided. According to one aspect of the system, the system is used to perform scrambling code detection of eight (8) primary cells (each scrambling code's X-component being spaced sixteen (16) chips apart) in a group. According to another aspect of the system, a single scrambling code generator is used to generate a master scrambling code. The master scrambling code is then used to create individual scrambling codes which are used in correlation with received signals to detect in parallel which one of the eight (8) possible primary cells in the group transmitted the received signals.

Abstract translation: 提供了一种用于检测和识别发送扰码的基站或小区的身份的系统。 根据该系统的一个方面，该系统用于对组（8个）主小区进行扰码检测（每个扰码的X分量间隔十六（16）个码片）。 根据系统的另一方面，使用单个扰码发生器来产生主扰码。 然后，主扰码用于产生与接收信号相关使用的各个扰码，并行检测组中八（8）个可能的主小区中的哪一个发送接收信号。

公开(公告)号：US20030054774A1

公开(公告)日：2003-03-20

申请号：US10015544

申请日：2001-12-12

Applicant: Quicksilver Technology, Inc.

Inventor： Robert T. Plunkett ,  Ghobad Heidari ,  Paul L. Master

IPC: H04B001/40

CPC classification number: H04L29/06 ,  G06F15/7867 ,  H04L69/329 ,  H04W52/0209 ,  H04W88/02 ,  Y02D10/12 ,  Y02D10/13 ,  Y02D70/142 ,  Y02D70/144

Abstract: The present invention concerns a new category of integrated circuitry and a new methodology for adaptive or reconfigurable computing. The exemplary IC embodiment includes a plurality of heterogeneous computational elements coupled to an interconnection network. The plurality of heterogeneous computational elements include corresponding computational elements having fixed and differing architectures, such as fixed architectures for different functions such as memory, addition, multiplication, complex multiplication, subtraction, configuration, reconfiguration, control, input, output, and field programmability. In response to configuration information, the interconnection network is operative in real-time to configure and reconfigure the plurality of heterogeneous computational elements for a plurality of different functional modes, including linear algorithmic operations, non-linear algorithmic operations, finite state machine operations, memory operations, and bit-level manipulations. The various fixed architectures are selected to comparatively minimize power consumption and increase performance of the adaptive computing integrated circuit, particularly suitable for mobile, hand-held or other battery-powered computing applications. In an exemplary embodiment, some or all of the computational elements are alternately configured to implement two or more functions including a system acquisition function.

Abstract translation: 本发明涉及一种新类型的集成电路和用于自适应或可重新配置计算的新方法。 示例性IC实施例包括耦合到互连网络的多个异构计算元件。 多个异构计算元件包括具有固定和不同架构的对应的计算元件，例如用于不同功能的固定架构，例如存储器，加法，乘法，复数乘法，减法，配置，重配置，控制，输入，输出和现场可编程性。 响应于配置信息，互连网络可实时操作以配置和重新配置用于多种不同功能模式的多个异构计算元件，包括线性算法运算，非线性算法运算，有限状态机操作，存储器 操作和位级操作。 选择各种固定架构以相对最小化功率消耗并增加自适应计算集成电路的性能，特别适用于移动，手持或其他电池供电的计算应用。 在示例性实施例中，部分或全部计算元件被交替地配置为实现包括系统获取功能的两个或多个功能。