公开(公告)号：US20030171908A1

公开(公告)日：2003-09-11

申请号：US10247186

申请日：2002-09-18

Applicant: Quickturn Design Systems, Inc.

Inventor： William John Schilp ,  Pramodini Arramreddy ,  Krishna Babu Bangera ,  Makarand Yashwant Joshi

IPC: G06F017/50

CPC classification number: G06F17/5022

Abstract: A fully synthesizeable Simulation Control Module (SCM) controls and monitors the simulation of a design under test (DUT). A clock generator within the SCM and a Software clock facility residing on the host workstation are responsible for providing the clocks for the DUT. The SCM and the hardware clock facility are dynamically generated at build time to suit the needs of the DUT. They maximize performance by automatically generating clock waveforms for designs containing multiple asynchronous clocks, thereby decreasing the frequency of accelerator-workstation interaction. The software clock facility has the ability to directly drive the DUT and is responsible for managing the simulation time and clock parameters. The SCM is also responsible for monitoring an abort condition such as a trigger to execute an external software model. The SCM and the clock facilities allow the hardware accelerator to efficiently support multiple asynchronous clock domains, execution of external software models and co-simulation.

Abstract translation: 完全可综合仿真控制模块（SCM）可以对被测设计（DUT）的仿真进行控制和监控。 SCM内的时钟发生器和驻留在主机工作站上的软件时钟设备负责为DUT提供时钟。 SCM和硬件时钟设备在构建时动态生成，以满足DUT的需要。 它们通过为包含多个异步时钟的设计自动生成时钟波形来最大限度地提高性能，从而降低加速器 - 工作站交互的频率。 软件时钟设备能够直接驱动DUT，并负责管理仿真时间和时钟参数。 SCM还负责监视中止条件，例如执行外部软件模型的触发器。 SCM和时钟设备允许硬件加速器有效地支持多个异步时钟域，执行外部软件模型和协同仿真。