公开(公告)号：US20020107682A1

公开(公告)日：2002-08-08

申请号：US10107741

申请日：2002-03-26

Applicant: Quickturn Design Systems, Inc.

Inventor： Stephen P. Sample ,  Michael R. D'Amour ,  Thomas S. Payne

IPC: G06F009/455

CPC classification number: G06F11/261 ,  G06F17/5027

Abstract: A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system. a network of internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.

Abstract translation: 用于电子电路或系统的物理仿真的系统包括数据输入工作站，其中用户可以输入表示电路或系统配置的数据。 该数据被转换成适合于编程具有丰富互连架构的可编程门元件阵列的形式。 规定用于外部连接VLSI设备或用户电路或系统的其他部分。 通过利用可编程门阵列中未使用的电路路径可以获得内部探测互连网络。

公开(公告)号：US20020161568A1

公开(公告)日：2002-10-31

申请号：US09922113

申请日：2001-08-02

Applicant: Quickturn Design Systems, Inc.

Inventor： Stephen P. Sample ,  Mikhail Bershteyn ,  Michael R. Butts ,  Jerry R. Bauer

IPC: G06F009/455

CPC classification number: G01R31/2853 ,  G01R31/31717 ,  G06F17/5027 ,  Y10S370/916

Abstract: A hardware emulation system is disclosed which reduces hardware cost by time-multiplexing multiple design signals onto physical logic chip pins and printed circuit board. The reconfigurable logic system of the present invention comprises a plurality of reprogrammable logic devices, and a plurality of reprogrammable interconnect devices. The logic devices and interconnect devices are interconnected together such that multiple design signals share common I/O pins and circuit board traces. A logic analyzer for a hardware emulation system is also disclosed. The logic circuits necessary for executing logic analyzer functions is programmed into the programmable resources in the logic chips of the emulation system.

Abstract translation: 公开了一种硬件仿真系统，其通过将多个设计信号时分复用到物理逻辑芯片引脚和印刷电路板上来降低硬件成本。 本发明的可重构逻辑系统包括多个可重编程逻辑器件和多个可重新编程的互连器件。 逻辑器件和互连器件互连在一起，使得多个设计信号共享公共I / O引脚和电路板迹线。 还公开了一种用于硬件仿真系统的逻辑分析仪。 执行逻辑分析器功能所需的逻辑电路被编程到仿真系统的逻辑芯片中的可编程资源中。

公开(公告)号：US20020095649A1

公开(公告)日：2002-07-18

申请号：US09949006

申请日：2001-09-06

Applicant: Quickturn Design Systems, Inc.

Inventor： Stephen P. Sample ,  Michael R. Butts

IPC: G06F017/50

CPC classification number: H03K19/17736 ,  G06F15/7867 ,  G06F17/5027

Abstract: A logic chip useful for emulation and prototyping of integrated circuits. The logic chip comprises a plurality of logic elements, which is divided into a plurality of subsets of logic elements. The logic chip further comprises a plurality of first level interconnects. The plurality of first level interconnects interconnect one of the plurality of subsets of logic elements, thereby forming a plurality of first level logical units. The plurality of first level logical units is divided into a plurality of subsets of first level logical units. The logic chip also comprises a plurality of second level interconnects. The second level interconnects interconnect one of the plurality of subsets of first level logic units, thereby forming a plurality of second level logic units. The logic chip also comprises a third level interconnect. The third level interconnect interconnects the plurality of second level logic units, thereby forming a third level logic

Abstract translation: 用于集成电路仿真和原型设计的逻辑芯片。 逻辑芯片包括多个逻辑元件，其被分成多个逻辑元件子集。 逻辑芯片还包括多个第一级互连。 多个第一级互连互连多个逻辑元件子集中的一个，从而形成多个第一级逻辑单元。 多个第一级逻辑单元被分成多个第一级逻辑单元子集。 逻辑芯片还包括多个第二级互连。 第二级互连将第一级逻辑单元的多个子集中的一个互连，从而形成多个第二级逻辑单元。 逻辑芯片还包括第三级互连。 第三级互连将多个第二级逻辑单元互连，从而形成第三级逻辑

公开(公告)号：US20040148153A1

公开(公告)日：2004-07-29

申请号：US10373558

申请日：2003-02-24

Applicant: Quickturn Design Systems, Inc.

Inventor： Platon Beletsky ,  Alon Kfir ,  Tsair-Chin Lin

IPC: G06F009/455

CPC classification number: G06F17/5027

Abstract: A method and apparatus for debugging circuit designs having random access memory therein. The circuit design is emulated on a hardware logic emulator. The RAM emulated by the emulator can be rewound to a previous state, and then replayed. The RAM emulated by the emulator can also be reconstructed to a state the RAM maintained at some point during a trace window.

公开(公告)号：US20020049578A1

公开(公告)日：2002-04-25

申请号：US09879658

申请日：2001-06-11

Applicant: Quickturn Design Systems, Inc.

Inventor： Takahide Ohkami

IPC: G06F009/45

CPC classification number: G06F17/5022

Abstract: A system is provided to increase the accessibility of registers and memories in a user's design undergoing functional verification in a hardware-assisted design verification system. A packet-based protocol is used to perform data transfer operations between a host workstation and a hardware accelerator for loading data to and unloading data from the registers and memories in a target design under verification (DUV) during logic simulation. The method and apparatus synthesizes interface logic into the DUV to provide for greater access to the registers and memories in the target DUV which is simulated with the assistance of the hardware accelerator.

Abstract translation: 提供了一种系统，用于在硬件辅助设计验证系统中进行功能验证的用户设计中增加寄存器和存储器的可访问性。 在逻辑模拟期间，基于分组的协议用于在主机工作站和硬件加速器之间执行数据传输操作，用于在目标设计（DUV）期间将数据加载到数据和从寄存器和存储器中卸载数据。 该方法和装置将接口逻辑合成到DUV中以提供对在硬件加速器的辅助下模拟的目标DUV中的寄存器和存储器的更大访问。

公开(公告)号：US20030212539A1

公开(公告)日：2003-11-13

申请号：US10459340

申请日：2003-06-11

Applicant: Quickturn Design Systems, Inc.

Inventor： William F. Beausoleil ,  Tak-Kwong Ng ,  Helmut Roth ,  Peter Tannenbaum ,  N. James Tomassetti

IPC: G06F009/455

CPC classification number: G06F17/5027

Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of nullcascadenull connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.

Abstract translation: 处理器集群作为仿真引擎互连，使得处理器共享输入和数据堆栈，并行地完成结果的设置和存储，但是一个评估单元的输出连接到下一个评估单元的输入。 一组“级联”连接提供对中间值的访问。 通过点击一个处理器的中间值，并将它们馈送到下一个处理器，可以实现显着的仿真加速。

公开(公告)号：US20030084414A1

公开(公告)日：2003-05-01

申请号：US10246788

申请日：2002-09-17

Applicant: Quickturn Design Systems, Inc.

Inventor： Platon Beletsky

IPC: G06F017/50

CPC classification number: G06F17/5027 ,  G06F17/505 ,  G06F17/5054

Abstract: A method for resynthesizing gated clocks in a clock cone of a logic design having more than one input clock where the logic design will be implemented in a hardware logic emulation system. By resynthesizing the gated clocks, timing in the circuit becomes predictable. In the method, predicting logic that predicts which edges of said at least two input clocks may cause a hold time violation on a gated clock is generated. Then, the outputs from the predicting logic are connected to a gated clock resolution circuit, which outputs the resynthesized clock.

Abstract translation: 一种用于在具有多于一个输入时钟的逻辑设计的时钟锥中重新合成门控时钟的方法，其中逻辑设计将在硬件逻辑仿真系统中实现。 通过重新合成门控时钟，电路中的时序变得可预测。 在该方法中，产生预测所述至少两个输入时钟的哪些边缘的逻辑，可能导致门控时钟上的保持时间违规。 然后，来自预测逻辑的输出连接到门控时钟分辨率电路，其输出再合成时钟。

公开(公告)号：US20040123258A1

公开(公告)日：2004-06-24

申请号：US10669095

申请日：2003-09-23

Applicant: Quickturn Design Systems, Inc.

Inventor： Michael R. Butts

IPC: G06F017/50

CPC classification number: G06F17/5027

Abstract: A design verification system utilizing programmable logic devices having varying numbers of logic processors, macro processors, memory processors and general purpose processors programmed therein is disclosed. These various processors can execute Boolean functions, macro operations, memory operations, and other computer instructions. This avoids either the need to implement logic or the need to compile the design into many gate-level Boolean logic operations for logic processors. Improved efficiency in the form of lower cost, lower power and/or higher speeds are the result when verifying certain types of designs.

Abstract translation: 公开了一种使用具有不同数量的逻辑处理器，宏处理器，存储器处理器和其中编程的通用处理器的可编程逻辑器件的设计验证系统。 这些各种处理器可以执行布尔函数，宏操作，存储器操作和其他计算机指令。 这避免了实现逻辑的需要或将逻辑处理器的设计编入许多门级布尔逻辑运算的需要。 在验证某些类型的设计时，会以更低的成本，更低的功率和/或更高的速度的形式提高效率。

公开(公告)号：US20030171908A1

公开(公告)日：2003-09-11

申请号：US10247186

申请日：2002-09-18

Applicant: Quickturn Design Systems, Inc.

Inventor： William John Schilp ,  Pramodini Arramreddy ,  Krishna Babu Bangera ,  Makarand Yashwant Joshi

IPC: G06F017/50

CPC classification number: G06F17/5022

Abstract: A fully synthesizeable Simulation Control Module (SCM) controls and monitors the simulation of a design under test (DUT). A clock generator within the SCM and a Software clock facility residing on the host workstation are responsible for providing the clocks for the DUT. The SCM and the hardware clock facility are dynamically generated at build time to suit the needs of the DUT. They maximize performance by automatically generating clock waveforms for designs containing multiple asynchronous clocks, thereby decreasing the frequency of accelerator-workstation interaction. The software clock facility has the ability to directly drive the DUT and is responsible for managing the simulation time and clock parameters. The SCM is also responsible for monitoring an abort condition such as a trigger to execute an external software model. The SCM and the clock facilities allow the hardware accelerator to efficiently support multiple asynchronous clock domains, execution of external software models and co-simulation.

Abstract translation: 完全可综合仿真控制模块（SCM）可以对被测设计（DUT）的仿真进行控制和监控。 SCM内的时钟发生器和驻留在主机工作站上的软件时钟设备负责为DUT提供时钟。 SCM和硬件时钟设备在构建时动态生成，以满足DUT的需要。 它们通过为包含多个异步时钟的设计自动生成时钟波形来最大限度地提高性能，从而降低加速器 - 工作站交互的频率。 软件时钟设备能够直接驱动DUT，并负责管理仿真时间和时钟参数。 SCM还负责监视中止条件，例如执行外部软件模型的触发器。 SCM和时钟设备允许硬件加速器有效地支持多个异步时钟域，执行外部软件模型和协同仿真。

公开(公告)号：US20030154458A1

公开(公告)日：2003-08-14

申请号：US10356919

申请日：2003-01-30

Applicant: Quickturn Design Systems, Inc.

Inventor： Michael R. Butts ,  Ming Yang Wang ,  Swey-Yan Shei ,  Alon Kfir

IPC: G06F017/50

CPC classification number: G06F17/5027

Abstract: A circuit for an emulation system that has a logic element having a RAM, lookup table, optional delay element and flip-flop/latch. The flip-flop/latch may behave as a flip-flop or as a latch and has separate set and reset signals. The delay element inserts a selectable amount of delay into the data path of the logic element in order to reduce race time problems. The logic elements may be combined to share input signals so as to increase the size of the RAM. The improved circuit also has a playback memory used to store up to a a plurality of copies of sampled data from a logic element so that emulation data can be played back for debugging purposes. Multiple read ports coupled to the logic elements permit a user to read out data from the logic elements during emulation in a time multiplexed manner. The input/output pins may be time multiplexed to carry multiple signals, unidirectionally or bidirectionally.