公开(公告)号：US20030212539A1

公开(公告)日：2003-11-13

申请号：US10459340

申请日：2003-06-11

Applicant: Quickturn Design Systems, Inc.

Inventor： William F. Beausoleil ,  Tak-Kwong Ng ,  Helmut Roth ,  Peter Tannenbaum ,  N. James Tomassetti

IPC: G06F009/455

CPC classification number: G06F17/5027

Abstract: Clusters of processors are interconnected as an emulation engine such that processors share input and data stacks, and the setup and storing of results are done in parallel, but the output of one evaluation unit is connected to the input of the next evaluation unit. A set of nullcascadenull connections provides access to the intermediate values. By tapping intermediate values from one processor, and feeding them to the next, a significant emulation speedup is achieved.

Abstract translation: 处理器集群作为仿真引擎互连，使得处理器共享输入和数据堆栈，并行地完成结果的设置和存储，但是一个评估单元的输出连接到下一个评估单元的输入。 一组“级联”连接提供对中间值的访问。 通过点击一个处理器的中间值，并将它们馈送到下一个处理器，可以实现显着的仿真加速。