公开(公告)号：US20040148153A1

公开(公告)日：2004-07-29

申请号：US10373558

申请日：2003-02-24

Applicant: Quickturn Design Systems, Inc.

Inventor： Platon Beletsky ,  Alon Kfir ,  Tsair-Chin Lin

IPC: G06F009/455

CPC classification number: G06F17/5027

Abstract: A method and apparatus for debugging circuit designs having random access memory therein. The circuit design is emulated on a hardware logic emulator. The RAM emulated by the emulator can be rewound to a previous state, and then replayed. The RAM emulated by the emulator can also be reconstructed to a state the RAM maintained at some point during a trace window.