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公开(公告)号：US5874967A
公开(公告)日：1999-02-23
申请号：US931926
申请日：1997-09-17
CPC分类号： G06T1/20 , G06T11/00 , G06T15/503
摘要： A graphics system comprising a format processor for receiving display data including pixel data and color-blending information for at least two (2) separate display layers, a color blender and color processors. The pixel data includes color information for the display layers. The color-blending information determines weighting factors for use in blending the colors of the display layers. The format processor outputs separate streams of pixel data, one for each display layer, as well as the weighting factors. Each stream of pixel data outputted by the processor is inputted into a corresponding color processor that assigns colors to a particular display layer according to the color information in the corresponding pixel data. The color blender blends the colors assigned to the display layers according to the weighting factors.
摘要翻译： 一种图形系统，包括用于接收包括用于至少两（2）个分立显示层的像素数据和颜色混合信息的显示数据的格式处理器，彩色混合器和彩色处理器。 像素数据包括显示层的颜色信息。 颜色混合信息确定用于混合显示层的颜色的加权因子。 格式处理器输出单独的像素数据流，每个显示层一个以及加权因子。 由处理器输出的每个像素数据流被输入到根据相应像素数据中的颜色信息将颜色分配给特定显示层的相应颜色处理器。 混色机根据加权因子混合分配给显示层的颜色。
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2.发明授权Graphics display subsystem that allows per pixel double buffer display rejection 失效图形显示子系统允许每像素双缓冲显示拒绝
公开(公告)号：US5629723A
公开(公告)日：1997-05-13
申请号：US528866
申请日：1995-09-15
摘要： A graphics display subsystem that allows rejection of double buffer display of pixel data in a graphics layer is provided. The subsystem has a memory containing a plurality of pixels represented by binary bits, wherein each pixel is divided into two or more sub-pixel fields, and wherein one or more bits of a particular sub-pixel field of a given pixel are set to a predetermined double buffer reject value when the given pixel corresponds to a single buffer display application. A double buffer reject circuit compares one or more bits of a double buffer sub-pixel field of a given pixel with a predetermined double buffer reject value to determine equality of the one or more bits and the predetermined value, wherein the given pixel is represented by binary bits and wherein the given pixel is divided into two or more sub-pixel fields including the double buffer sub-pixel field. The double buffer reject circuit receives a buffer select signal selecting one of the two or more sub-pixel fields of the given pixel to be accessed during a current display frame. In response, the double buffer reject circuit accesses the selected sub-pixel field of the given pixel when the buffer select signal does not select the double buffer sub-pixel field or when the buffer select signal selects the double buffer sub-pixel field and the comparison does not show equality, and further the double buffer reject circuit accesses one of the two or more sub-pixel fields of the given pixel that is not the double buffer sub-pixel field when the buffer select signal selects the double buffer sub-pixel field and the comparison shows equality. A digital-to-analog converter in communication with the double buffer reject circuit receives the pixel data contained in the sub-pixel field accessed by the double buffer reject circuit and converts the pixel data into analog video signals for driving a monitor display device.
摘要翻译： 提供允许拒绝图形层中的像素数据的双缓冲器显示的图形显示子系统。 子系统具有包含由二进制位表示的多个像素的存储器，其中每个像素被分成两个或更多个子像素场，并且其中给定像素的特定子像素场的一个或多个位被设置为 当给定像素对应于单个缓冲器显示应用时，预定的双缓冲器拒绝值。 双缓冲器拒绝电路将给定像素的双缓冲器子像素场的一个或多个比特与预定的双缓冲区拒绝值进行比较，以确定一个或多个比特和预定值的相等性，其中给定像素由 二进制位，并且其中给定像素被分成包括双缓冲器子像素场的两个或多个子像素场。 双缓冲器抑制电路接收在当前显示帧期间选择要访问的给定像素的两个或多个子像素场中的一个的缓冲器选择信号。 作为响应，当缓冲器选择信号不选择双缓冲器子像素场时，或者当缓冲器选择信号选择双缓冲器子像素场时，双缓冲区拒绝电路访问给定像素的选择子像素场，并且 比较不显示相等性，并且当缓冲器选择信号选择双缓冲器子像素时，双缓冲区拒绝电路进一步访问给定像素中不是双缓冲器子像素场的两个或更多个子像素场中的一个 字段和比较显示相等。 与双缓冲器抑制电路通信的数模转换器接收由双缓冲器抑制电路访问的子像素场中包含的像素数据，并将像素数据转换为用于驱动监视器显示设备的模拟视频信号。
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公开(公告)号：US4661955A
公开(公告)日：1987-04-28
申请号：US692804
申请日：1985-01-18
IPC分类号： G06F11/10 , G06F12/16 , G11C11/401 , G11C29/00 , G11C29/42 , H03M13/00 , H03M13/03 , H03M13/19
CPC分类号： G06F11/1028 , H03M13/033 , H03M13/19 , G11B2020/183
摘要： An extended error code particularly applicable to a code that can correct any number of errors in one sub-field but can only detect the existence of any number of errors in two sub-fields. If the initial pass of the data through the error correction code indicates an uncorrected error, the data is complemented and restored in the memory and then reread. The retrieved data is recomplemented and again passed through the error correction code. If an uncorrected error persists, then a bit-by-bit comparision is performed between the originally read data and the retrieved complemented data to isolate the hard fails in the memory. The bits in the sub-field associated with the hard fail are then sequentially changed and then the changed data word is passed through the error correction code. A wrong combination is detected by the error correction code. The sequential changing continues until the bits in the sub-field associated with the hard fail match the originally stored data, in which case the error correction code can correct the remaining errors in the remaining sub-fields.
摘要翻译： 扩展错误代码特别适用于可以纠正一个子字段中任何数量的错误但只能检测两个子字段中任何数量的错误的存在的代码。 如果通过纠错码的数据的初始通过指示未校正的错误，则在存储器中对数据进行补充和恢复，然后重新读取。 检索的数据被重新补充，并再次通过纠错码。 如果未校正的错误仍然存在，则在原始读取的数据和检索到的补码数据之间进行逐位比较，以隔离存储器中的硬故障。 然后顺序地改变与硬故障相关联的子场中的位，然后改变的数据字通过纠错码。 错误校正码检测出错误的组合。 顺序改变继续，直到与硬故障相关联的子场中的位与原始存储的数据匹配，在这种情况下，纠错码可以校正剩余子场中的剩余误差。
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4.发明授权Programmable serializer using multiplexer and programmable address counter for providing flexiblity in scanning sequences and width of data 失效可编程串行器使用多路复用器和可编程地址计数器，提供扫描顺序和数据宽度的灵活性
公开(公告)号：US5689731A
公开(公告)日：1997-11-18
申请号：US475545
申请日：1995-06-07
申请人： Roderick Michael P. West , Hiroyuki Ando , Stephen B. Barrett , Peter Casavant , Edward K. Evans , Daniel Liguori , David Litten
发明人： Roderick Michael P. West , Hiroyuki Ando , Stephen B. Barrett , Peter Casavant , Edward K. Evans , Daniel Liguori , David Litten
CPC分类号： G09G5/395 , G06F13/4018
摘要： A programmable serializer comprising a multi-bit input port, a multi-bit output port, at least one multiplexer and at least one programmable address counter corresponding to the multiplexer for generating a sequence of multiplexer data input addresses that are inputted into the multiplexer address input. The multiplexer has an output connected to the multi-bit output port, an address input and a plurality of data input channels having addresses. Each data input channel is connected to a corresponding bit of the multi-bit input port. At least one data input channel is coupled to the multiplexer output when the corresponding address of the data input channel is applied to the address input. The programmable address counter receives and stores an initial address value, an address increment value and a count value and generates a sequence of addresses based on these values. The initial address value represents the multiplexer data channel that is to be initially coupled to the multiplexer output. The address increment value represents the increment that must be added to a current address in order to reach a next address. The count value represents the number of address that must be generated by the counter prior to restarting the sequence at the initial address value.
摘要翻译： 一种可编程串行器，包括多位输入端口，多位输出端口，至少一个多路复用器和至少一个可编程地址计数器，其对应于多路复用器，用于产生输入到多路复用器地址输入端的多路复用器数据输入地址序列 。 复用器具有连接到多位输出端口的输出，地址输入和具有地址的多个数据输入通道。 每个数据输入通道连接到多位输入端口的相应位。 当数据输入通道的相应地址被应用于地址输入时，至少一个数据输入通道耦合到多路复用器输出。 可编程地址计数器接收并存储初始地址值，地址增量值和计数值，并且基于这些值生成地址序列。 初始地址值表示要最初耦合到多路复用器输出的多路复用器数据通道。 地址增量值表示必须添加到当前地址以便到达下一个地址的增量。 计数值表示在初始地址值重新启动序列之前必须由计数器产生的地址数。
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公开(公告)号：US07013441B2
公开(公告)日：2006-03-14
申请号：US10605379
申请日：2003-09-26
申请人： Jeanne P. Bickford , Edward K. Evans , Sean Horner , Raymond J. Rosner , Andrew Wienick , Joseph Yoder
发明人： Jeanne P. Bickford , Edward K. Evans , Sean Horner , Raymond J. Rosner , Andrew Wienick , Joseph Yoder
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： A method and system for predicting manufacturing yield for a proposed integrated circuit The method includes: in the order recited: (a) providing a multiplicity of different integrated circuit library elements in a design database, each library element linked to a corresponding normalization factor in the design database; (b) selecting library elements from the design database to include in a proposed design for the integrated circuit; (c) generating an equivalent circuit count of the proposed design based on the normalization factors and a count of each different library element included in the proposed design; and (d) calculating a predicted manufacturing yield based on the equivalent circuit count, a predicted density of manufacturing defects and an area of the proposed integrated circuit chip.
摘要翻译： 一种用于预测所提出的集成电路的制造产量的方法和系统。该方法包括：按照所述的顺序：（a）在设计数据库中提供多个不同的集成电路库元件，每个库元件链接到相应的归一化因子 设计数据库; （b）从设计数据库中选择库元素以包含在集成电路的拟议设计中; （c）基于归一化因子和所提出的设计中包括的每个不同的库元素的计数产生所提出的设计的等效电路数; 以及（d）基于等效电路数，制造缺陷的预测密度和所提出的集成电路芯片的面积来计算预计制造产量。
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6.发明授权Control function employing a requesting master id and a data address to qualify data access within an integrated system 有权控制功能采用请求主标识和数据地址来限定集成系统内的数据访问公开(公告)号：US06851056B2
公开(公告)日：2005-02-01
申请号：US10125527
申请日：2002-04-18
CPC分类号： G06F21/6218 , G06F12/1483 , G06F21/78 , G06F21/85 , G06F2221/2129 , G06F2221/2141 , G06F2221/2143
摘要： An access control function for an integrated system is provided which determines data access based on the master id of a requesting master within the system and the address of the data. The access control function can be inserted, for example, into the data transfer path between bus control logic and one or more slaves. In addition to determining whether to grant access to the data, the access control function can further qualify the access by selectively implementing encryption and decryption of data, again dependent on the data authorization level for the particular functional master initiating the request for data.
摘要翻译： 提供了一种用于集成系统的访问控制功能，其基于系统内的请求主机的主机ID和数据的地址来确定数据访问。 访问控制功能可以插入到例如总线控制逻辑和一个或多个从站之间的数据传输路径中。 除了确定是否允许对数据的访问之外，访问控制功能还可以通过选择性地实现数据的加密和解密来进一步限定访问，这又取决于启动数据请求的特定功能主体的数据授权级别。
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