公开(公告)号：US12229587B2

公开(公告)日：2025-02-18

申请号：US18621936

申请日：2024-03-29

Applicant: REBELLIONS INC.

Inventor： Hongyun Kim ,  Chang-Hyo Yu ,  Yoonho Boo

IPC: G06F9/48 ,  G06F9/54 ,  G06F12/0831

Abstract: A command processor determines whether a command descriptor describing a current command is in a first format or in a second format, wherein the first format includes a source memory address pointing to a memory area in a shared memory having a binary code to be accessed according to direct memory access (DMA) scheme, and the second format includes one or more object indices, a respective one of the one or more object indices indicating an object in an object database. If the command descriptor describing the current command is in the second format, the command processor converts a format of the command descriptor to the first format, generates one or more task descriptors describing neural network model tasks based on the command descriptor in the first format, and distributes the one or more task descriptors to the one or more neural processors.

公开(公告)号：US12099915B2

公开(公告)日：2024-09-24

申请号：US17659067

申请日：2022-04-13

Applicant: REBELLIONS INC.

Inventor： Yoonho Boo

IPC: G06N3/04 ,  G06N3/08

CPC classification number: G06N3/04 ,  G06N3/08

Abstract: A method for quantizing a deep neural network is provided, which includes extracting first statistical information on output values of a first normalization layer included in the deep neural network, determining a discretization interval associated with input values of a subsequent layer of the first normalization layer by using the extracted first statistical information, and quantizing the input values of the subsequent layer into discretized values having the determined discretization interval.

公开(公告)号：US20240211742A1

公开(公告)日：2024-06-27

申请号：US18597728

申请日：2024-03-06

Applicant: Rebellions Inc.

Inventor： Jinseok Kim ,  Kyeongryeol Bong ,  Jinwook Oh ,  Yoonho Boo

IPC: G06N3/063 ,  G06F9/54 ,  G06F12/084

CPC classification number: G06N3/063 ,  G06F9/544 ,  G06F12/084

Abstract: A neural core, a neural processing device including same and a method for lauding data of a neural processing device are provided. The neural core comprises a processing unit configured to perform operations, an L0 memory configured to store input data and an LSU configured to perform a load task and a store task of data between the processing unit and the L0 memory, wherein the LSU comprises a local memory load unit configured to transmit the input data in the L0 memory to the processing unit, and the local memory load unit comprises a target decision module configured to identify and retrieve the input data in the L0 memory, a transformation logic configured to transform the input data and thereby generate transformed data and an output FIFO configured to receive the transformed data and transmit the transformed data to the processing unit in the received order.

公开(公告)号：US20240330041A1

公开(公告)日：2024-10-03

申请号：US18621936

申请日：2024-03-29

Applicant: REBELLIONS INC.

Inventor： Hongyun Kim ,  Chang-Hyo Yu ,  Yoonho Boo

IPC: G06F9/48 ,  G06F9/54 ,  G06F12/0831

CPC classification number: G06F9/4856 ,  G06F9/544 ,  G06F12/0835

Abstract: A command processor determines whether a command descriptor describing a current command is in a first format or in a second format, wherein the first format includes a source memory address pointing to a memory area in a shared memory having a binary code to be accessed according to direct memory access (DMA) scheme, and the second format includes one or more object indices, a respective one of the one or more object indices indicating an object in an object database. If the command descriptor describing the current command is in the second format, the command processor converts a format of the command descriptor to the first format, generates one or more task descriptors describing neural network model tasks based on the command descriptor in the first format, and distributes the one or more task descriptors to the one or more neural processors.

公开(公告)号：US11954584B2

公开(公告)日：2024-04-09

申请号：US18322519

申请日：2023-05-23

Applicant: Rebellions Inc.

Inventor： Jinseok Kim ,  Kyeongryeol Bong ,  Jinwook Oh ,  Yoonho Boo

IPC: G06F9/54 ,  G06N3/063 ,  G06F12/084

CPC classification number: G06N3/063 ,  G06F9/544 ,  G06F12/084

Abstract: A neural core, a neural processing device including same and a method for lauding data of a neural processing device are provided. The neural core comprises a processing unit configured to perform operations, an L0 memory configured to store input data and an LSU configured to perform a load task and a store task of data between the processing unit and the L0 memory, wherein the LSU comprises a local memory load unit configured to transmit the input data in the L0 memory to the processing unit, and the local memory load unit comprises a target decision module configured to identify and retrieve the input data in the L0 memory, a transformation logic configured to transform the input data and thereby generate transformed data and an output FIFO configured to receive the transformed data and transmit the transformed data to the processing unit in the received order.

公开(公告)号：US20240013038A1

公开(公告)日：2024-01-11

申请号：US18322519

申请日：2023-05-23

Applicant: Rebellions Inc.

Inventor： Jinseok Kim ,  Kyeongryeol Bong ,  Jinwook Oh ,  Yoonho Boo

IPC: G06N3/063 ,  G06F9/54

CPC classification number: G06N3/063 ,  G06F9/544

Abstract: A neural core, a neural processing device including same and a method for lauding data of a neural processing device are provided. The neural core comprises a processing unit configured to perform operations, an L0 memory configured to store input data and an LSU configured to perform a load task and a store task of data between the processing unit and the L0 memory, wherein the LSU comprises a local memory load unit configured to transmit the input data in the L0 memory to the processing unit, and the local memory load unit comprises a target decision module configured to identify and retrieve the input data in the L0 memory, a transformation logic configured to transform the input data and thereby generate transformed data and an output FIFO configured to receive the transformed data and transmit the transformed data to the processing unit in the received order.