公开(公告)号：US20240142519A1

公开(公告)日：2024-05-02

申请号：US18470911

申请日：2023-09-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazushi NAKAMURA

IPC: G01R31/317

CPC classification number: G01R31/31727

Abstract: In scan testing of semiconductor devices, instantaneous power consumption in both shift and capture modes is efficiently reduced. The scan chain is provided with circuit blocks 1 to 4. Each of the temporary storage flip-flops F1 to F3 is connected between one of the two circuit blocks. Clock generating circuit 10 outputs a clock signal CLK used for the scan test. The clock gating cells GC1 to GC4 takes the clock signal CLK and provides the clock signals CLK1 to CLK4 to circuit blocks 1 to 4 and the clock signals CLK1 to CLK3 to the temporary storage flip-flops F1 to F3. The control circuit 20 controls the clock gating cells GC1 to GC4 so as to operate the circuit blocks 1 to 4 at differing timings from the input-side one by one and simultaneously operate each circuit block and a temporary storage flip-flop connected to the output of each circuit block.