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公开(公告)号：US10650949B2
公开(公告)日：2020-05-12
申请号：US16116681
申请日：2018-08-29
Applicant: Renesas Electronics Corporation
Inventor： Hironori Asano , Noriaki Matsuno
Abstract: A semiconductor device capable of reducing in size thereof and suppressing degradation in the characteristics of circuit components is provided. The semiconductor device includes an LC circuit comprised of a spiral inductor provided over a semiconductor substrate and a capacitive element coupled with the spiral inductor. The spiral inductor includes a central area encircled with a metal wiring and a peripheral area other than the central area. The capacitive element is formed in an upper-layer or a lower-layer position corresponding to the peripheral area other than the central area.
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公开(公告)号：US10361665B2
公开(公告)日：2019-07-23
申请号：US15881207
申请日：2018-01-26
Applicant: Renesas Electronics Corporation
Inventor： Noriaki Matsuno
Abstract: A semiconductor integrated circuit includes a low-noise amplifier circuit, a transformer, and an ESD protection circuit. The low-noise amplifier circuit amplifies a radio signal that is supplied to an input terminal. The transformer includes a first winding and a second winding and functions as an input impedance matching circuit for the low-noise amplifier circuit, in which at least one end of the second winding is connected to the input terminal of the low-noise amplifier circuit. The ESD protection circuit is connected to a center tap of the first winding.
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公开(公告)号：US09722641B2
公开(公告)日：2017-08-01
申请号：US15017608
申请日：2016-02-06
Applicant: Renesas Electronics Corporation
Inventor： Noriaki Matsuno
IPC: H04B1/04
CPC classification number: H04B1/0458 , H04B1/0475
Abstract: A semiconductor device (10) includes a transmitting circuit (12) that converts transmission data into a transmission signal with a specified frequency, an amplifier (13) that amplifies a power of the transmission signal, a matching circuit (14) that converts the transmission signal from a balanced signal to an unbalanced signal, and a filter circuit (14) that restricts a frequency band of the transmission signal. The matching circuit includes a primary inductor and a secondary indictor, the filter circuit includes an inductor for a filter, and the primary inductor, the secondary indictor and the inductor for a filter are wound substantially concentrically on one plane.
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公开(公告)号：US20160087624A1
公开(公告)日：2016-03-24
申请号：US14959568
申请日：2015-12-04
Applicant: Renesas Electronics Corporation
Inventor： Noriaki Matsuno
IPC: H03K17/16 , H03K17/693
CPC classification number: H03K17/161 , H03K17/693
Abstract: A high frequency switch circuit including a first terminal, a second terminal, a bias terminal, n (n is an integer more than one) number of transistors connected in series in an order from a first transistor to an nth transistor from said first terminal to said second terminal, first to nth nodes respectively connected to back gates of said first to nth transistors, and n number of resistance elements connected in series in an order from a first resistance element to an nth resistance element from said bias terminal to said nth node, wherein said first resistance element is connected between said bias terminal and said first node, and a kth resistance element (k=2 to n) is connected between said (k−1)th node and said kth node.
Abstract translation: 一种高频开关电路，包括从第一晶体管到第n晶体管的从第一端子到第一端子的顺序串联连接的晶体管的第一端子，第二端子，偏置端子，n（n是多于一个的整数）个晶体管 所述第二端子，分别连接到所述第一至第n晶体管的后栅极的第一至第n节点和从所述偏置端子到所述第n节点的从第一电阻元件到第n电阻元件的顺序串联连接的n个电阻元件 ，其中所述第一电阻元件连接在所述偏置端子和所述第一节点之间，并且第k电阻元件（k = 2至n）连接在所述第（k-1）个节点和所述第k个节点之间。
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公开(公告)号：US09209801B2
公开(公告)日：2015-12-08
申请号：US14062645
申请日：2013-10-24
Applicant: Renesas Electronics Corporation
Inventor： Noriaki Matsuno
IPC: H03K17/687 , H03K17/693
CPC classification number: H03K17/161 , H03K17/693
Abstract: N (n is an integer more than one) number of transistors are connected in series in an order from a first transistor to an nth transistor from a first terminal to a second terminal. First to nth nodes are connected to gates of the first to nth transistors. N number of resistance elements are connected in series in an order from a first resistance element to an nth resistance element from a bias terminal to the nth node. The first resistance element is connected between said bias terminal and said first node, and the kth resistance element (k=2 to n) is connected between the (k−1)th node and the kth node. Thus, a high frequency switch circuit can reduce an area of the whole gate bias resistances.
Abstract translation: N（n是多于一个的整数）晶体管的数量从第一晶体管到第n晶体管的顺序从第一端子连接到第二端子。 第一至第n个节点连接到第一至第n晶体管的栅极。 N个电阻元件从第一电阻元件到第n电阻元件从偏置端子到第n个节点的顺序串联连接。 第一电阻元件连接在所述偏置端子和所述第一节点之间，并且第k电阻元件（k = 2至n）连接在第（k-1）个节点和第k个节点之间。 因此，高频开关电路可以减小整个栅极偏置电阻的面积。
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Patent Agency Ranking
公开(公告)号：US20140118053A1
公开(公告)日：2014-05-01
申请号：US14062645
申请日：2013-10-24
Applicant: Renesas Electronics Corporation
Inventor： Noriaki Matsuno
IPC: H03K17/687
CPC classification number: H03K17/161 , H03K17/693
Abstract: N (n is an integer more than one) number of transistors are connected in series in an order from a first transistor to an nth transistor from a first terminal to a second terminal. First to nth nodes are connected to gates of the first to nth transistors. N number of resistance elements are connected in series in an order from a first resistance element to an nth resistance element from a bias terminal to the nth node. The first resistance element is connected between said bias terminal and said first node, and the kth resistance element (k=2 to n) is connected between the (k−1)th node and the kth node. Thus, a high frequency switch circuit can reduce an area of the whole gate bias resistances.
Abstract translation: N（n是多于一个的整数）晶体管的数量从第一晶体管到第n晶体管的顺序从第一端子连接到第二端子。 第一至第n个节点连接到第一至第n晶体管的栅极。 N个电阻元件从第一电阻元件到第n电阻元件从偏置端子到第n个节点的顺序串联连接。 第一电阻元件连接在所述偏置端子和所述第一节点之间，并且第k电阻元件（k = 2至n）连接在第（k-1）个节点和第k个节点之间。 因此，高频开关电路可以减小整个栅极偏置电阻的面积。
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公开(公告)号：US10693476B2
公开(公告)日：2020-06-23
申请号：US15950968
申请日：2018-04-11
Applicant: Renesas Electronics Corporation
Inventor： Yuichi Maruyama , Noriaki Matsuno
Abstract: Increases of circuit scale and power consumption are suppressed while frequency deviation is kept within a predetermined allowable range. A semiconductor device according to an embodiment includes a variable load capacity circuit including a plurality of load capacity elements coupled in parallel to one end of a crystal resonator and a plurality of switches that are respectively serially coupled to the load capacity elements, and a switch control unit that controls ON/OFF of the switches on the basis of information to be an index of frequency deviation due to temperature change of a frequency signal obtained by oscillating the crystal resonator. The switch control unit changes the number of switches that will be turned ON among the plurality of switches so that an absolute value of the frequency deviation becomes small when the information is not included in a predetermined allowable range.
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公开(公告)号：US10263576B2
公开(公告)日：2019-04-16
申请号：US15875602
申请日：2018-01-19
Applicant: Renesas Electronics Corporation
Inventor： Noriaki Matsuno
Abstract: A semiconductor integrated circuit includes a transformer that includes a first winding and a second winding, a low-noise amplifier circuit that includes an input terminal in which at least one end of the second winding of the transformer is connected to the input terminal; and a switch that is provided between the one end and another end of the second winding of the transformer. The switch is opened and the transformer functions as an input impedance matching circuit for the low-noise amplifier circuit in a period in which a reception signal is supplied to the first winding of the transformer. On the other hand, the switch is closed and the transformer is caused to become an element including a predetermined capacitance in a period in which another circuit connected to the predetermined node operates.
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公开(公告)号：US10148295B2
公开(公告)日：2018-12-04
申请号：US15642740
申请日：2017-07-06
Applicant: Renesas Electronics Corporation
Inventor： Noriaki Matsuno
IPC: H04B1/04
Abstract: A semiconductor device (10) includes a transmitting circuit (12) that converts transmission data into a transmission signal with a specified frequency, an amplifier (13) that amplifies a power of the transmission signal, a matching circuit (14) that converts the transmission signal from a balanced signal to an unbalanced signal, and a filter circuit (14) that restricts a frequency band of the transmission signal. The matching circuit includes a primary inductor and a secondary inductor, the filter circuit includes an inductor for a filter, and the primary inductor, the secondary indictor and the inductor for a filter are wound substantially concentrically on one plane.
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公开(公告)号：US09923525B2
公开(公告)日：2018-03-20
申请号：US15043593
申请日：2016-02-14
Applicant: Renesas Electronics Corporation
Inventor： Noriaki Matsuno
CPC classification number: H03F1/52 , H01L27/0255 , H01L27/0296 , H03F1/565 , H03F3/195 , H03F3/245 , H03F2200/222 , H03F2200/294 , H03F2200/387 , H03F2200/444 , H03F2200/451 , H03F2200/534 , H03F2200/541
Abstract: A semiconductor integrated circuit includes a low-noise amplifier circuit, a transformer, and an ESD protection circuit. The low-noise amplifier circuit amplifies a radio signal that is supplied to an input terminal. The transformer includes a first winding and a second winding and functions as an input impedance matching circuit for the low-noise amplifier circuit, in which at least one end of the second winding is connected to the input terminal of the low-noise amplifier circuit. The ESD protection circuit is connected to a center tap of the first winding.
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