公开(公告)号：US20230387901A1

公开(公告)日：2023-11-30

申请号：US18303960

申请日：2023-04-20

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takayuki OOTANI

IPC: H03K5/131 ,  G06F11/16

CPC classification number: H03K5/131 ,  G06F11/1641 ,  G06F11/1695

Abstract: A technique for enhancing reliability is provided. A semiconductor device includes a main device which operates in a delayed lockstep mode, a sub device which operates in parallel to the main device in a delayed lockstep mode, a delay circuit which delays an output of the main device, a switching circuit which switches the main device to the sub device according to failure information of the main device.

公开(公告)号：US20230064905A1

公开(公告)日：2023-03-02

申请号：US17878256

申请日：2022-08-01

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Takayuki OOTANI

IPC: G06F11/16 ,  G06F11/20

Abstract: When one of CPUs that perform a lock step operation fails and the failure type is an SW failure, the semiconductor device copies information held by an SR and a GR of the CPU operating normally to the CPU with the SW failure, thereby continuing a process without stopping the lock step operation. On the other hand, when the failure type is an HW failure, the failed CPU is stopped to continue the process with only the normal CPU.