公开(公告)号：US20190006364A1

公开(公告)日：2019-01-03

申请号：US15985280

申请日：2018-05-21

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kazuo SAKAMOTO ,  Toshiaki ITO

IPC: H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/0928 ,  H01L21/823807 ,  H01L21/823892 ,  H01L27/0259

Abstract: According to one embodiment, a semiconductor device includes a shallow P-well, a shallow N-well, a shallow P-well, and a shallow N-well formed in regions different from one another, a deep N-well formed in a part deeper than the shallow P-well and the shallow N-well, and a base material, and further includes a first transistor formed in a part of the shallow P-well and the shallow N-well on the side of the principal surface, and a second transistor formed in a part of the shallow P-well and the shallow N-well on the side of the principal surface, in which the shallow N-well is formed in such a way as to surround the peripheral edge of the region of the shallow P-well.