公开(公告)号：US20140152379A1

公开(公告)日：2014-06-05

申请号：US14089489

申请日：2013-11-25

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Toshio FUJIMOTO ,  Takashi ITO

IPC: H01L49/02 ,  H02M3/07

CPC classification number: H01L28/60 ,  G11C5/145 ,  H01L23/5223 ,  H01L27/0222 ,  H01L27/11526 ,  H01L27/11573 ,  H01L28/86 ,  H01L28/90 ,  H01L29/94 ,  H01L2924/0002 ,  H02M3/073 ,  H01L2924/00

Abstract: There is provided a capacitor with a reduced layout area. A capacitor has an electrode EL1 formed by using a first polysilicon layer, an electrode EL2 formed by using a second polysilicon layer over the first polysilicon layer, and electrodes EL3 to EL6 formed by using second through fifth metal wiring layers over the second polysilicon layer. An N-type well and the electrode EL1 make up a capacitor element 11, the electrodes EL1, EL2 make up a capacitor element 12, and the electrodes EL3 to EL6 make up a capacitor element 13. The capacitor elements 11 to 13 are coupled in parallel between terminals T1, T2.

Abstract translation: 提供了具有减小的布局面积的电容器。 电容器具有通过使用第一多晶硅层形成的电极EL1，在第一多晶硅层上使用第二多晶硅层形成的电极EL2以及通过在第二多晶硅层上使用第二至第五金属布线层形成的电极EL3至EL6。 N型阱，电极EL1构成电容器元件11，电极EL1，EL2构成电容器元件12，电极EL3〜EL6构成电容器元件13.电容器元件11〜13耦合在 端子T1，T2之间平行。