公开(公告)号：US20040137649A1

公开(公告)日：2004-07-15

申请号：US10437911

申请日：2003-05-15

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Takeshi Kishida ,  Shigenori Kido

IPC: H01L021/00

CPC classification number: H01L23/544 ,  G03F7/70633 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A photolithography step is carried out for exposing/etching a resist film in an etching step. Thereafter a superposition inspection step employing a superposed layer superposition mark and a resist film superposition mark is carried out with a superposition inspection apparatus. In this step, an applied mask confirmation step is simultaneously carried out with the superposition inspection apparatus. Thus, it is possible to provide a method of fabricating a semiconductor device including a superposition inspection step, capable of efficiently confirming an applied mask and improving the fabrication yield for the semiconductor device.

Abstract translation: 在蚀刻步骤中进行曝光/蚀刻抗蚀剂膜的光刻步骤。 此后，使用重叠检查装置进行使用叠加层叠加标记和抗蚀剂膜叠加标记的叠加检查步骤。 在该步骤中，与叠加检查装置同时进行应用的掩模确认步骤。 因此，可以提供一种制造包括叠加检查步骤的半导体器件的方法，其能够有效地确认所施加的掩模并且提高半导体器件的制造成品率。