公开(公告)号：US20040250165A1

公开(公告)日：2004-12-09

申请号：US10649682

申请日：2003-08-28

Applicant: RENESAS TECHNOLOGY CORP.

Inventor： Tetsushi Tanizaki

IPC: H02H003/05

CPC classification number: G11C29/48 ,  G11C2029/3202

Abstract: A boundary scan cell in a semiconductor memory device (memory core) is provided corresponding to each terminal for performing a boundary scan test. A test controller and a read/write control circuit cause the boundary scan cell to latch input write data in a late write operation, until a next write cycle of the write cycle at which the write data was input from the terminal.

Abstract translation: 半导体存储器件（存储器核心）中的边界扫描单元对应于每个用于执行边界扫描测试的端子被提供。 测试控制器和读/写控制电路使得边界扫描单元在迟写操作中锁存输入写入数据，直到写入数据从终端输入的写周期的下一个写周期为止。