公开(公告)号：US12112818B2

公开(公告)日：2024-10-08

申请号：US17856744

申请日：2022-07-01

Applicant: Synopsys, Inc.

Inventor： Harold Pilo ,  Shishir Kumar

IPC: G11C7/00 ,  G11C29/30 ,  G11C29/40 ,  G11C29/32

CPC classification number: G11C29/40 ,  G11C29/30 ,  G11C2029/3202

Abstract: A method of using on-chip circuitry to test a memory of a chip is provided. The method including, in a capture stage, receiving, at a first n-bit compression structure including n first stage latches corresponding to each bit of the first n-bit compression structure, a value at each respective first stage latch for each of n memory addresses of the memory, such that each respective first stage latch receives a respective value from a memory address of the memory, n being an integer greater than one, and in the capture stage, passing the values from each respective first stage latch through compression logic of the first n-bit compression structure to output a single compressed address value, providing the single compressed address value to a second stage latch of the first n-bit compression structure.

公开(公告)号：US20240295604A1

公开(公告)日：2024-09-05

申请号：US18590333

申请日：2024-02-28

Applicant: STMicroelectronics International N.V.

Inventor： Gianluca TORTORA ,  Mario BARONE

IPC: G01R31/3185 ,  G11C29/32

CPC classification number: G01R31/318536 ,  G01R31/318541 ,  G11C29/32 ,  G11C2029/3202

Abstract: An integrated circuit includes a sequential logic circuit and a circuit configured to change operation as a function of state output signals provided by state flip-flops of the sequential logic circuit. With a test mode signal asserted, a test circuit writes and reads the content of the state flip-flops in order to test the operation of the sequential logic circuit. A processing system includes at least one storage circuit interposed between the circuit and a respective state output signal. Each storage circuit receives the respective state output signal and provides a modified state signal to the circuit. When the test mode signal is de-asserted, the storage circuit provides the received state output signal in a transparent manner to the circuit and stores the received state output signal to a storage element. When the test mode signal is asserted, the storage circuit provides the stored state output signal to the circuit.

公开(公告)号：US12007440B1

公开(公告)日：2024-06-11

申请号：US17847421

申请日：2022-06-23

Applicant: Cadence Design Systems, Inc.

Inventor： Puneet Arora ,  Subhasish Mukherjee ,  Sarthak Singhal ,  Christos Papameletis ,  Brian Foutz ,  Krishna V Chakravadhanula ,  Ankit Bandejia ,  Norman Card

IPC: G01R31/3185 ,  G01R31/317 ,  G06F11/267 ,  G06F30/333 ,  G11C29/32

CPC classification number: G01R31/318536 ,  G01R31/318547 ,  G01R31/31704 ,  G01R31/3185 ,  G01R31/318558 ,  G01R31/318563 ,  G01R31/318583 ,  G06F11/267 ,  G06F30/333 ,  G11C29/32 ,  G11C2029/3202

Abstract: This disclosure relates scan chain stitching. In one example, scan chain elements from a scan chain element space can be received for a scan chain partition. The scan chain elements can be grouped based on scan chain element grouping criteria to form scan chain groups. Scan chain data identifying a number of scan chains for the scan chain partition can be received. The scan chains can be scan chain balanced across the scan chain groups to assign each scan chain to one of the scan chain groups. The scan chain elements associated with each scan chain of the scan chains can be scan chain element balanced. Scan chain elements for each associated scan chain can be connected to form a scan chain data test path during a generation of scan chain circuitry in response to the scan chain element balancing.

公开(公告)号：US20180024189A1

公开(公告)日：2018-01-25

申请号：US15214767

申请日：2016-07-20

Applicant: International Business Machines Corporation

Inventor： Steven M. Douskey ,  Michael J. Hamilton ,  Amanda R. Kaufer ,  Phillip A. Senum

IPC: G01R31/3177 ,  G01R31/3185

CPC classification number: G01R31/3187 ,  G01R31/31853 ,  G11C29/12 ,  G11C29/32 ,  G11C29/44 ,  G11C29/4401 ,  G11C2029/3202

Abstract: A method and circuit for implementing register array repair using Logic Built In Self Test (LBIST), and a design structure on which the subject circuit resides are provided. Register array repair includes identifying and creating a list of any repairable Register Arrays (RAs) that effect an LBIST fail result. Next a repair solution is detected for each of the repairable Register Arrays (RAs) isolating a failing location for the detected repair solution for each array.

公开(公告)号：US09865361B2

公开(公告)日：2018-01-09

申请号：US15140242

申请日：2016-04-27

Applicant: Invecas, Inc.

Inventor： Thomas Chadwick ,  Kevin W. Gorman ,  Nancy Pratt

IPC: G11C29/00 ,  G11C29/38 ,  G11C29/44

CPC classification number: G11C29/38 ,  G11C29/44 ,  G11C2029/3202

Abstract: A memory diagnostic system comprises a test engine and a miscompare logic. The test engine provides test instructions with expected data to a memory under test (“MUT”). The MUT processes such test patterns and outputs the results of such test patterns as stored data. The miscompare logic has local miscompare logics and a global miscompare logic. Each of the local miscompare logics compares a predefined range of bits of the expected data with a corresponding predefined range of bits of the stored data. One or more miscompare flags are generated for one or more miscompares determined by the local miscompare logics. The global miscompare logic monitors the one or more miscompare flags. When a total number of the miscompare flags exceeds a threshold number, the global miscompare logic generates a pause signal to the local miscompare logics to capture a current state of the local miscompare logics.

公开(公告)号：US09767918B2

公开(公告)日：2017-09-19

申请号：US15282932

申请日：2016-09-30

Applicant: Rambus Inc.

Inventor： Craig Hampel ,  Mark Horowitz

IPC: G06F12/00 ,  G11C29/12 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0846 ,  G06F13/16 ,  G11C5/04 ,  G11C7/10 ,  G11C29/00 ,  G06F3/06 ,  G06F12/0897 ,  G11C29/32

CPC classification number: G11C29/1201 ,  G06F3/0611 ,  G06F3/0614 ,  G06F3/0647 ,  G06F3/0688 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0851 ,  G06F12/0897 ,  G06F13/1684 ,  G06F2212/2022 ,  G06F2212/205 ,  G06F2212/3042 ,  G06F2212/608 ,  G11C5/04 ,  G11C7/10 ,  G11C7/1003 ,  G11C29/12 ,  G11C29/12015 ,  G11C29/32 ,  G11C29/76 ,  G11C2029/3202 ,  Y02D10/13 ,  Y02D10/14

Abstract: Volatile memory devices may be on a first memory module that is coupled to a memory controller by a first signal path. A nonvolatile memory device may be on a second memory module that is coupled to the first memory module by a second signal path. A memory transaction for the nonvolatile memory device may be transferred from the memory controller to at least one of the volatile memory devices using the first signal path and data associated with the memory transaction is to be written from at least one of the volatile memory devices to the nonvolatile memory device using the second signal path and a control signal. A defect circuit may generate the control signal in view of a detection of a defect in the nonvolatile memory device based on a comparison of a test value read from a memory location to a stored value.

公开(公告)号：US09739833B2

公开(公告)日：2017-08-22

申请号：US14874502

申请日：2015-10-05

Applicant: International Business Machines Corporation

Inventor： Jixiang Hou ,  Hailong Li ,  Li Min Liu ,  Yin Peng Lu ,  Liudi Wang

IPC: G01R31/28 ,  G01R31/3177 ,  G11C29/32

CPC classification number: G01R31/3177 ,  G11C29/32 ,  G11C2029/3202

Abstract: A method for constructing a scan chain for a memory sequential test, including determining an input boundary register of the memory; determining a number N of test vectors required according to the type of the memory input pins to which the input boundary register is connected; arranging the scan chain based on the number N, such that in the scan chain, upstream of the input boundary register and immediately adjacent to the input boundary register, there are at least (N−1) continuous non-boundary registers; and setting control signals of the input boundary register and the (N−1) non-boundary registers to make them receive scan test input as test vectors under memory sequential test mode.

公开(公告)号：US09689924B2

公开(公告)日：2017-06-27

申请号：US14980994

申请日：2015-12-28

Applicant: STMICROELECTRONICS INTERNATIONAL N.V.

Inventor： Anirudha Kulkarni ,  Jasvir Singh

IPC: G01R31/3185 ,  G01R31/3187 ,  G11C29/26 ,  G01R31/319 ,  G11C29/12 ,  G11C29/32 ,  G01R31/3177 ,  G01R31/317

CPC classification number: G01R31/318563 ,  G01R31/31724 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318533 ,  G01R31/318536 ,  G01R31/318538 ,  G01R31/318552 ,  G01R31/318558 ,  G01R31/318572 ,  G01R31/318594 ,  G01R31/318597 ,  G01R31/3187 ,  G01R31/31922 ,  G11C29/12 ,  G11C29/12015 ,  G11C29/26 ,  G11C29/32 ,  G11C2029/3202

Abstract: An integrated circuit is configured to receive a test clock input and includes circuitry configured to generate test clocks from the test clock input, and test circuitry configured to use the test clocks in a test mode.

公开(公告)号：US09678154B2

公开(公告)日：2017-06-13

申请号：US14528554

申请日：2014-10-30

Applicant: QUALCOMM Incorporated

Inventor： Animesh Datta ,  Qi Ye ,  Steven James Dillen

IPC: G01R31/28 ,  G01R31/317 ,  G01R31/3177 ,  H03K5/133 ,  H03K5/134 ,  G11C7/10 ,  G11C29/32 ,  G01R31/3185

CPC classification number: G01R31/31725 ,  G01R31/31727 ,  G01R31/3177 ,  G01R31/318541 ,  G11C7/1057 ,  G11C7/1066 ,  G11C29/32 ,  G11C2029/3202 ,  H03K5/133 ,  H03K5/134

Abstract: In one embodiment, a method for signal delay in a scan path comprises, in a scan mode, delaying a scan signal in the scan path by propagating the scan signal through a plurality of delay devices coupled in series, wherein a first one of the delay devices is powered by a first voltage, a second one of the delay devices is powered by a second voltage, and the second voltage is greater than the first voltage. The method also comprises, in a functional mode, disabling the delay devices.

公开(公告)号：US09666301B2

公开(公告)日：2017-05-30

申请号：US14488171

申请日：2014-09-16

Applicant: QUALCOMM Incorporated

Inventor： Venugopal Boynapalli ,  Kashyap Ramachandra Bellur ,  Prabaharan Balu ,  Bilal Zafar ,  Alex Dongkyu Park ,  Sei Seung Yoon

IPC: G01R31/28 ,  G11C29/08 ,  G11C29/32 ,  G11C8/16 ,  G11C29/20

CPC classification number: G11C29/08 ,  G11C8/16 ,  G11C29/20 ,  G11C29/32 ,  G11C2029/3202

Abstract: An example scannable register file includes a plurality of memory cells and, a shift phase of a scan test shifts data bits from a scan input through the plurality of memory cells to a scan output. The shifting can be performed by, on each clock cycle, reading one of the plurality of memory cells to supply the scan out and writing one of the plurality of memory cells with the data bit on a scan input. To perform sequential reads and writes on each clock cycle, the scannable register can generate a write clock that, during the shift phase, is inverted from the clock used for functional operation. The write clock is generated without glitches so that unintended writes do not occur. Scannable register files can be integrated with scan-based testing (e.g., using automatic test pattern generation) of other modules in an integrated circuit.