公开(公告)号：US20140055192A1

公开(公告)日：2014-02-27

申请号：US13927182

申请日：2013-06-26

Applicant: RF Micro Devices, Inc.

Inventor： Andrew P. Ritenour ,  Dan Schwob

IPC: H03K17/08

CPC classification number: H03K17/08 ,  H03K17/063

Abstract: A circuit topology for limiting saturation current in power transistors is disclosed. The circuit topology includes a normally-on transistor and a normally-off transistor coupled in series. A limiter circuit is coupled between a gate of the normally-on transistor and a source of the normally-off transistor for limiting the steady-state maximum gate-to-source voltage VGS of the normally-on transistor, which in turn limits the saturation current that flows through the normally-on transistor and the normally-off transistor.

Abstract translation: 公开了用于限制功率晶体管中的饱和电流的电路拓扑。 电路拓扑包括一个常闭晶体管和一个常闭晶体管串联耦合。 限制电路耦合在常通晶体管的栅极和常关晶体管的源极之间，用于限制常导通晶体管的稳态最大栅极 - 源极电压VGS，这又限制了饱和 流经常通晶体管和常关晶体管的电流。