公开(公告)号：US09530853B2

公开(公告)日：2016-12-27

申请号：US14627340

申请日：2015-02-20

Applicant: RF Micro Devices, Inc.

Inventor： Haldane S. Henry ,  Eunki Hong ,  Charles S. Whitman

IPC: H01L21/44 ,  H01L29/47 ,  H01L29/812 ,  H01L29/66 ,  H01L21/285 ,  H01L29/20 ,  H01L21/02

CPC classification number: H01L29/475 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28581 ,  H01L29/2003 ,  H01L29/66863 ,  H01L29/812

Abstract: A semiconductor device with reduced leakage current and a method of making the same is disclosed. The semiconductor device includes a substrate having a device layer, a dielectric layer, and a gate metal opening within the dielectric layer between a source contact and a gate contact. A first metal layer is disposed within the gate metal opening, and a second metal layer is disposed directly onto the second metal layer, wherein the second metal layer is oxidized and has a thickness that ranges from about 4 Angstroms to about 20 Angstroms to limit a leakage current of a total gate periphery to between around 0.1 μA/mm and around 50 μA/mm. A current carrying layer is disposed on the second metal layer. In one embodiment, the first metal layer is nickel (Ni), the second metal layer is palladium (Pd), and the current carrying layer is gold (Au).

Abstract translation: 公开了一种具有减小的漏电流的半导体器件及其制造方法。 半导体器件包括在源极接触和栅极接触之间的介电层内具有器件层，电介质层和栅极金属开口的衬底。 第一金属层设置在栅极金属开口内，并且第二金属层直接设置在第二金属层上，其中第二金属层被氧化并且具有在约4埃至约20埃的范围内以限制 总门外围的漏电流在约0.1μA/ mm到约50μA/ mm之间。 载流层设置在第二金属层上。 在一个实施例中，第一金属层是镍（Ni），第二金属层是钯（Pd），载流层是金（Au）。

公开(公告)号：US20150255560A1

公开(公告)日：2015-09-10

申请号：US14627340

申请日：2015-02-20

Applicant: RF Micro Devices, Inc.

Inventor： Haldane S. Henry ,  Eunki Hong ,  Charles S. Whitman

IPC: H01L29/47 ,  H01L21/02 ,  H01L29/20 ,  H01L21/285 ,  H01L29/812 ,  H01L29/66

CPC classification number: H01L29/475 ,  H01L21/02244 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/28581 ,  H01L29/2003 ,  H01L29/66863 ,  H01L29/812

Abstract: A semiconductor device with reduced leakage current and a method of making the same is disclosed. The semiconductor device includes a substrate having a device layer, a dielectric layer, and a gate metal opening within the dielectric layer between a source contact and a gate contact. A first metal layer is disposed within the gate metal opening, and a second metal layer is disposed directly onto the second metal layer, wherein the second metal layer is oxidized and has a thickness that ranges from about 4 Angstroms to about 20 Angstroms to limit a leakage current of a total gate periphery to between around 0.1 μA/mm and around 50 μA/mm. A current carrying layer is disposed on the second metal layer. In one embodiment, the first metal layer is nickel (Ni), the second metal layer is palladium (Pd), and the current carrying layer is gold (Au).

Abstract translation: 公开了一种具有减小的漏电流的半导体器件及其制造方法。 半导体器件包括在源极接触和栅极接触之间的介电层内具有器件层，电介质层和栅极金属开口的衬底。 第一金属层设置在栅极金属开口内，并且第二金属层直接设置在第二金属层上，其中第二金属层被氧化并且具有在约4埃至约20埃的范围内以限制 总门外围的漏电流在约0.1μA/ mm到约50μA/ mm之间。 载流层设置在第二金属层上。 在一个实施例中，第一金属层是镍（Ni），第二金属层是钯（Pd），载流层是金（Au）。