公开(公告)号：US11764682B2

公开(公告)日：2023-09-19

申请号：US17684393

申请日：2022-03-01

Applicant: RICHTEK TECHNOLOGY CORP.

Inventor： Yung-Jen Chen

IPC: H02M3/158 ,  H02M1/00 ,  H02M1/32

CPC classification number: H02M3/1586 ,  H02M1/0003 ,  H02M1/0016 ,  H02M1/32 ,  H02M3/158 ,  H02M3/1582

Abstract: A buck converter includes a quick response circuit, a compensator coupled to an output node, an interleaving logic circuit coupled to the compensator, a plurality of on-time generators, a plurality of OR gates coupled to the corresponding on-time generator, a plurality of power stages coupled to the corresponding OR gates, a plurality of inductors and an output capacitor. Each on-time generator is coupled to the interleaving logic circuit, an input node and the output node. The quick response circuit includes a voltage droop sensor coupled to the output node, a load frequency sensor coupled to the output node, a quick response signal generator coupled to the voltage droop sensor, a maximum quick response signal generator coupled to the voltage droop sensor and the load frequency sensor, an AND gate coupled to the quick response signal generator, the maximum quick response signal generator and the plurality of OR gates.

公开(公告)号：US20230127211A1

公开(公告)日：2023-04-27

申请号：US17684393

申请日：2022-03-01

Applicant: RICHTEK TECHNOLOGY CORP.

Inventor： Yung-Jen Chen

IPC: H02M3/158 ,  H02M1/00

Abstract: A buck converter includes a quick response circuit, a compensator coupled to an output node, an interleaving logic circuit coupled to the compensator, a plurality of on-time generators, a plurality of OR gates coupled to the corresponding on-time generator, a plurality of power stages coupled to the corresponding OR gates, a plurality of inductors and an output capacitor. Each on-time generator is coupled to the interleaving logic circuit, an input node and the output node. The quick response circuit includes a voltage droop sensor coupled to the output node, a load frequency sensor coupled to the output node, a quick response signal generator coupled to the voltage droop sensor, a maximum quick response signal generator coupled to the voltage droop sensor and the load frequency sensor, an AND gate coupled to the quick response signal generator, the maximum quick response signal generator and the plurality of OR gates.