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公开(公告)号：US07065675B1
公开(公告)日：2006-06-20
申请号：US09850195
申请日：2001-05-08
IPC分类号： G06F11/00
CPC分类号： G01R31/318544 , G01R31/31705
摘要： A system and method for providing efficient block transfer operations through a test access port uses a Fastdata register. The Fastdata register, in part, emulates a pending process access bit (“PrAcc”) typically found in a Control register associated with the test access port. When a Fastdata access (either a Fastdata upload or a Fastdata download) is requested by a probe coupled to the test access port, the Fastdata register is serially coupled to a data register also associated with the test access port. With these registers so coupled and through the operation of the Fastdata register, downloading and uploading data can be accomplished using a single register operation.
摘要翻译： 通过测试访问端口提供有效的块传输操作的系统和方法使用Fastdata寄存器。 Fastdata寄存器部分地模拟通常在与测试访问端口相关联的控制寄存器中找到的待处理进程访问位（“PrAcc”）。 当FastData访问（Fastdata上传或Fastdata下载）被耦合到测试访问端口的探测器请求时，Fastdata寄存器串行耦合到也与测试访问端口相关联的数据寄存器。 通过这些寄存器如此耦合，并通过Fastdata寄存器的操作，可以使用单个寄存器操作来完成下载和上传数据。
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公开(公告)号：US07231551B1
公开(公告)日：2007-06-12
申请号：US09894831
申请日：2001-06-29
IPC分类号： G06F11/00
CPC分类号： G06F11/3636
摘要： A system accessible by a test access port controller via a test access port interface includes a data register. The data register is selectable based on an instruction register signal in the test access port interface. The instruction register signal is derived form an instruction register in the test access port controller. A shift register is connected to a data input and a data output in the test access port interface and to the data register. The operation of the shift register is controlled based on an indication of a state of a test access port controller state machine that is received over the test access port interface.
摘要翻译： 由测试访问端口控制器通过测试访问端口接口访问的系统包括数据寄存器。 数据寄存器可以根据测试访问端口接口中的指令寄存器信号进行选择。 指令寄存器信号从测试访问端口控制器中的指令寄存器导出。 移位寄存器连接到测试访问端口接口和数据寄存器中的数据输入和数据输出。 基于通过测试访问端口接口接收的测试访问端口控制器状态机的状态的指示来控制移位寄存器的操作。
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