公开(公告)号：US20200162096A1

公开(公告)日：2020-05-21

申请号：US16628977

申请日：2018-09-19

申请人： Radiawave Technologies Co., Ltd.

发明人： Xiaofeng GUO ,  Haigang FENG ,  Jon Sweat DUSTER ,  Yulin TAN ,  Ning ZHANG

IPC分类号： H03M1/46

摘要： The present disclosure relates to a capacitor array for an analog-to-digital converter, a successive approximation register analog-to-digital converter and a capacitor array board. The capacitor array includes a control logic generation circuit, a control code logic conversion circuit, a first sub-capacitor array and a second sub-capacitor array configured to form different regions of a high-order bit region and a low-order bit region. In the present disclosure, the capacitances of the second capacitor units are equal, so that the second capacitor units can be sequentially switched. Thus, no matter which bit in the second binary code changes, it will not cause a large number of the second capacitor units to switch together, thereby reducing conversion error. In addition, the capacitor array is divided in regions, which avoids the problem of a large number of parallel branches in case where only the second sub-capacitor array is arranged.

公开(公告)号：US20200259500A1

公开(公告)日：2020-08-13

申请号：US16758518

申请日：2018-11-06

申请人： Radiawave Technologies Co., Ltd.

发明人： Xiaofeng GUO ,  Haigang FENG ,  Jon Sweat DUSTER ,  Ning ZHANG ,  Yulin TAN

IPC分类号： H03M1/12 ,  H03M1/46

摘要： The present application discloses an N-bit hybrid-structure analog-to-digital converter and an integrated circuit chip including the same, including a pre-stage sampling capacitor array, a post-stage capacitor array and a comparator set and the pre-stage sampling capacitor array including a number of 2N−1 sets of first capacitor array units arranged in parallel, the first capacitor array unit including two sets of parallel capacitor strings, input terminals of parallel capacitor strings respectively being connected to and switchable between differential analog signals and first preset reference signals, output terminals of the parallel capacitor strings respectively being connected to input terminals of the comparator set, input terminals of the post-stage capacitor array respectively being connected to and switchable between output terminals of the comparator set and differential analog signals, output terminals of the post-stage capacitor array being configured as an output terminal of the analog-to-digital converter.

公开(公告)号：US20210313997A1

公开(公告)日：2021-10-07

申请号：US17350796

申请日：2021-06-17

申请人： Radiawave Technologies Co., Ltd.

发明人： Erkan ALPMAN ,  Xiaofeng GUO ,  Jon Sweat DUSTER ,  Yulin TAN ,  Ning ZHANG ,  Haigang FENG

IPC分类号： H03M1/46 ,  H03M1/12 ,  H03M7/16

摘要： Disclosed are an analog-to-digital converter error shaping circuit and a successive approximation analog-to-digital converter. The analog-to-digital converter error shaping circuit includes a decentralized capacitor array, a data weighted average module, a mismatch error shaping module, a control logic generation circuit, a digital filter and a decimator. The decentralized capacitor array includes two symmetrically arranged capacitor array units, each capacitor array unit includes a first sub-capacitor array of a high segment bit and a second sub-capacitor array of a low segment bit. The data weighted average module is configured to eliminate correlation between the first sub-capacitor array and an input signal, and the mismatch error shaping module is configured to eliminate correlation between the second sub-capacitor array and the input signal.

公开(公告)号：US20210266004A1

公开(公告)日：2021-08-26

申请号：US17318143

申请日：2021-05-12

申请人： Radiawave Technologies Co., Ltd.

发明人： Xiaofeng GUO ,  Erkan ALPMAN ,  Jon Sweat DUSTER ,  Haigang FENG ,  Ning ZHANG ,  Yulin TAN

IPC分类号： H03M1/10

摘要： A residue transfer loop, a successive approximation register analog-to-digital converter and a gain calibration method are disclosed. In particular, the residue transfer loop includes a sampling switch module, a logic controlling circuit, a residue holding capacitor module, a DAC capacitor array, a residue transfer module, a current rudder, a reset switch module and a charge sharing switch module. The logic controlling circuit sequentially outputs control signals according to preset time intervals in a preset period to control the reset switch module, the residue transfer module, the sampling switch module and the charge sharing switch module to work sequentially, thereby realizing a residue transfer.

公开(公告)号：US20200127675A1

公开(公告)日：2020-04-23

申请号：US16628984

申请日：2018-10-25

申请人： Radiawave Technologies Co., Ltd.

发明人： Xiaofeng GUO ,  Jon Sweat DUSTER ,  Haigang FENG ,  Ning ZHANG ,  Yulin TAN

IPC分类号： H03M1/10 ,  G05F1/56

摘要： The present disclosure relates to a mismatch calibration circuit for a current steering DAC of a SoC baseband chip and a SoC baseband chip. The mismatch calibration circuit includes current mirror compensation circuits, a calibration switching switch module, a calibration resistor, a voltage detection module, and a calibration control module. The resistance of the calibration resistor is 2N−1 times the resistance of the load resistor, where N is the number of MSBs. The number of the current mirror compensation circuits is equal to the number of the MSB current mirror branches. The current mirror compensation circuits are connected in parallel with the MSB current mirror branches to form current mirror parallel branches. The present disclosure minimizes mismatch error between the output currents of the current mirror array in the SoC baseband chip of 28 nm process or even a smaller process dimension, thereby improving conversion accuracy of the DAC.

公开(公告)号：US20210250037A1

公开(公告)日：2021-08-12

申请号：US17239626

申请日：2021-04-25

申请人： Radiawave Technologies Co., Ltd.

发明人： Xiaofeng GUO ,  Erkan ALPMAN ,  Jon Sweat DUSTER ,  Ning ZHANG ,  Yulin TAN ,  Haigang FENG

IPC分类号： H03M1/34

摘要： A reference voltage controlling circuit and an analog-to-digital converter are disclosed. The reference voltage controlling circuit includes a reference voltage generating circuit, a plurality of groups of sampling switching units and a logic controlling circuit. The DAC capacitor array switches the sampling switching units to a second positive reference voltage and a second negative reference voltage before starting sampling or conversion, and is charged and discharged with the second positive reference voltage and the second negative reference voltage to raise a voltage to a preset voltage. The sampling switching unit is switched to a first positive reference voltage and a first negative reference voltage to charge and discharge the DAC capacitor array to a target voltage. The rising of the voltage from the preset voltage to the target voltage is completed by the first positive reference voltage and the first negative reference voltage.