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公开(公告)号：US11677413B2
公开(公告)日：2023-06-13
申请号：US17508096
申请日：2021-10-22
发明人： Erkan Alpman , Xiaofeng Guo , Jon Sweat Duster , Yulin Tan , Ning Zhang , Haigang Feng
CPC分类号： H03M1/468 , G10L15/22 , H03G3/3005 , H03M1/462 , H04R3/00
摘要： Disclosed are an audio ADC for supporting voice wake-up and an electronic device. The audio ADC includes a programmable gain amplifier (PGA) having an input terminal for receiving an audio signal; a bypass switch having an input terminal for receiving an analog audio signal; and a successive approximation ADC having input terminals respectively connected to output terminals of the PGA and the bypass switch; the PGA gains and amplifies the audio signal, the bypass switch bypasses the PGA, and outputs the analog audio signal; the successive approximation performs analog-to-digital conversion with noise shaping on the analog audio signal after gain amplification at a first sampling rate/oversampling rate when the audio ADC is normal working, and turns off noise shaping when the audio ADC is sleep, performs analog-to-digital conversion on the analog audio signal output by the bypass switch at a second sampling rate/oversampling rate, and outputs to a DSP.
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公开(公告)号：US11621719B2
公开(公告)日：2023-04-04
申请号：US17508642
申请日：2021-10-22
发明人： Xiaofeng Guo , Erkan Alpman , Jon Sweat Duster , Yulin Tan , Haigang Feng , Ning Zhang
摘要： Disclosed are a pre-drive module of an analog-to-digital converter and an analog-to-digital conversion device. The pre-drive module includes a sampling capacitor; a controller configured to output a reset control signal, a pre-sampling control signal, and a sampling control signal according to a preset timing sequence; a reset module configured to reset the sampling capacitor upon receiving the reset control signal; a first auxiliary drive circuit configured to amplify an input analog signal and output to the sampling capacitor for sampling upon receiving the sample control signal; and a second auxiliary drive circuit. The controller is configured to output the pre-sampling control signal before outputting the sampling control signal, control the second auxiliary drive circuit to amplify the input analog signal, and output to the sampling capacitor for pre-sampling, and when a charging voltage of the sampling capacitor during pre-sampling reaches a preset voltage value, output the sampling control signal.
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公开(公告)号：US11342931B2
公开(公告)日：2022-05-24
申请号：US17239626
申请日：2021-04-25
发明人： Xiaofeng Guo , Erkan Alpman , Jon Sweat Duster , Ning Zhang , Yulin Tan , Haigang Feng
摘要： A reference voltage controlling circuit and an analog-to-digital converter are disclosed. The reference voltage controlling circuit includes a reference voltage generating circuit, a plurality of groups of sampling switching units and a logic controlling circuit. The DAC capacitor array switches the sampling switching units to a second positive reference voltage and a second negative reference voltage before starting sampling or conversion, and is charged and discharged with the second positive reference voltage and the second negative reference voltage to raise a voltage to a preset voltage. The sampling switching unit is switched to a first positive reference voltage and a first negative reference voltage to charge and discharge the DAC capacitor array to a target voltage. The rising of the voltage from the preset voltage to the target voltage is completed by the first positive reference voltage and the first negative reference voltage.
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公开(公告)号：US11057008B2
公开(公告)日：2021-07-06
申请号：US16628994
申请日：2018-09-18
发明人： Yigao Shao , Yulin Tan , Jon Sweat Duster , Haigang Feng , Ning Zhang
摘要： The present disclosure provides a power amplifier and an electrical device. The two-stage power amplifier architecture is tuned staggered before power combining. A previous stage matching network and its input matching are split into a cascaded staggered tuning, such that the center frequency is at frequency point 1 less than the design frequency point and frequency point 2 greater than design frequency point, and then the power combining stage is tuned at the design frequency point. At advanced process nodes (such as 65 nm or below), compared with the known architecture, in-band signal quality and out-of-band filtering effect of the power amplifier chip integrating this architecture will be better when using the same number of transformers (same area), the reliability will be better. Due to its good flatness within the band, this architecture is especially suitable for carrier aggregation communication occasions.
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公开(公告)号：US11973479B2
公开(公告)日：2024-04-30
申请号：US17508686
申请日：2021-10-22
发明人： Liuan Zhang , Yulin Tan , Jon Sweat Duster , Ning Zhang , Haigang Feng , Erkan Alpman
CPC分类号： H03G3/3005 , G11B20/10027 , H03G3/001 , H03M1/185 , G11B20/10037
摘要： Disclosed are a two-stage audio gain circuit based on analog-to-digital conversion and an audio terminal. The two-stage audio gain circuit includes a PGA configured to receive an analog audio signal and perform programmable gain amplification processing on the received analog audio signal; an ADC configured to convert the analog audio signal after the programmable gain amplification processing into a digital audio signal and output the digital audio signal; a first AGC gain unit configured to perform a first AGC processing on the digital audio signal and output a first gain adjustment value to the PGA, for the PGA to perform gain adjustment on the received analog audio signal; and a second AGC gain unit configured to perform a second AGC processing on the digital audio signal and output a second gain adjustment value to the PGA, for the PGA to perform gain adjustment on the received analog audio signal.
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公开(公告)号：US20210234535A1
公开(公告)日：2021-07-29
申请号：US17230107
申请日：2021-04-14
发明人： Liuan ZHANG , Haigang FENG , Yulin TAN , Ning ZHANG , Jon Sweat DUSTER
IPC分类号： H03H17/02
摘要： The present application discloses a filtering method and a filtering device of a filter, a filter and a storage medium. The method includes: obtaining a clock input signal and a clock output signal and comparing them, and determining a phase relationship between the clock input signal and the clock output signal according to a comparison result; determining a decimal deviation factor according to the phase relationship in determining that the phase relationship meets a preset condition; and filtering a sample input signal according to the decimal deviation factor to obtain a filtered sample output signal. The present application can obtain an accurate decimal deviation factor, by obtaining the phase relationship between the clock input signal and the clock output signal, in determining that the phase relationship meets a preset condition, and can adjust the sample input signal according to the decimal deviation factor to obtain a smooth sample output signal.
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7.发明授权公开(公告)号：US10965304B2
公开(公告)日：2021-03-30
申请号：US16758518
申请日：2018-11-06
发明人： Xiaofeng Guo , Haigang Feng , Jon Sweat Duster , Ning Zhang , Yulin Tan
摘要： The present application discloses an N-bit hybrid-structure analog-to-digital converter and an integrated circuit chip including the same, including a pre-stage sampling capacitor array, a post-stage capacitor array and a comparator set and the pre-stage sampling capacitor array including a number of 2N−1 sets of first capacitor array units arranged in parallel, the first capacitor array unit including two sets of parallel capacitor strings, input terminals of parallel capacitor strings respectively being connected to and switchable between differential analog signals and first preset reference signals, output terminals of the parallel capacitor strings respectively being connected to input terminals of the comparator set, input terminals of the post-stage capacitor array respectively being connected to and switchable between output terminals of the comparator set and differential analog signals, output terminals of the post-stage capacitor array being configured as an output terminal of the analog-to-digital converter.
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8.发明申请公开(公告)号：US20200162096A1
公开(公告)日：2020-05-21
申请号：US16628977
申请日：2018-09-19
发明人： Xiaofeng GUO , Haigang FENG , Jon Sweat DUSTER , Yulin TAN , Ning ZHANG
IPC分类号： H03M1/46
摘要： The present disclosure relates to a capacitor array for an analog-to-digital converter, a successive approximation register analog-to-digital converter and a capacitor array board. The capacitor array includes a control logic generation circuit, a control code logic conversion circuit, a first sub-capacitor array and a second sub-capacitor array configured to form different regions of a high-order bit region and a low-order bit region. In the present disclosure, the capacitances of the second capacitor units are equal, so that the second capacitor units can be sequentially switched. Thus, no matter which bit in the second binary code changes, it will not cause a large number of the second capacitor units to switch together, thereby reducing conversion error. In addition, the capacitor array is divided in regions, which avoids the problem of a large number of parallel branches in case where only the second sub-capacitor array is arranged.
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公开(公告)号：US11581900B2
公开(公告)日：2023-02-14
申请号：US17350796
申请日：2021-06-17
发明人： Erkan Alpman , Xiaofeng Guo , Jon Sweat Duster , Yulin Tan , Ning Zhang , Haigang Feng
摘要： Disclosed are an analog-to-digital converter error shaping circuit and a successive approximation analog-to-digital converter. The analog-to-digital converter error shaping circuit includes a decentralized capacitor array, a data weighted average module, a mismatch error shaping module, a control logic generation circuit, a digital filter and a decimator. The decentralized capacitor array includes two symmetrically arranged capacitor array units, each capacitor array unit includes a first sub-capacitor array of a high segment bit and a second sub-capacitor array of a low segment bit. The data weighted average module is configured to eliminate correlation between the first sub-capacitor array and an input signal, and the mismatch error shaping module is configured to eliminate correlation between the second sub-capacitor array and the input signal.
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公开(公告)号：US10804918B2
公开(公告)日：2020-10-13
申请号：US16628984
申请日：2018-10-25
发明人： Xiaofeng Guo , Jon Sweat Duster , Haigang Feng , Ning Zhang , Yulin Tan
摘要： The present disclosure relates to a mismatch calibration circuit for a current steering DAC of a SoC baseband chip and a SoC baseband chip. The mismatch calibration circuit includes current mirror compensation circuits, a calibration switching switch module, a calibration resistor, a voltage detection module, and a calibration control module. The resistance of the calibration resistor is 2N−1 times the resistance of the load resistor, where N is the number of MSBs. The number of the current mirror compensation circuits is equal to the number of the MSB current mirror branches. The current mirror compensation circuits are connected in parallel with the MSB current mirror branches to form current mirror parallel branches. The present disclosure minimizes mismatch error between the output currents of the current mirror array in the SoC baseband chip of 28 nm process or even a smaller process dimension, thereby improving conversion accuracy of the DAC.
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