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    Delivering specific contents to specific recipients using broadcast networks
    1.
    发明授权
    Delivering specific contents to specific recipients using broadcast networks 有权
    使用广播网络向特定收件人发送特定内容

    公开(公告)号：US08065742B2

    公开(公告)日：2011-11-22

    申请号：US11997904

    申请日：2005-10-30

    申请人： Rahul Shukla ,  Ajay Gupta ,  Vaibhav Rajan

    发明人： Rahul Shukla ,  Ajay Gupta ,  Vaibhav Rajan

    IPC分类号： G06F7/04

    CPC分类号： H04H20/28 ,  G02B6/29374 ,  H04H20/30 ,  H04H20/38 ,  H04H20/91 ,  H04H60/33 ,  H04H60/61 ,  H04H60/66 ,  H04H60/73 ,  H04H60/74 ,  H04H60/94 ,  H04H2201/20 ,  H04H2201/30 ,  H04N21/258 ,  H04N21/25891 ,  H04N21/434 ,  H04N21/44213 ,  H04N21/4508 ,  H04N21/4532 ,  H04N21/4722 ,  H04N21/4755

    摘要： Systems and methods for delivering specific contents to specific recipients using broadcast networks. The methods include receiving an AV signal of a broadcast program and supplementary content which contains a tag identifying a specific recipient and specific contents. The specific contents are encrypted with a public key associated with the specific recipient. The supplementary content is combined with the AV signal to form a data-augmented signal which is subsequently encoded and modulated with a carrier signal to form a transmit signal for broadcasting to receivers. Each receiver includes a supplementary decoder for extracting the supplementary content, decrypting the specific contents with a private key corresponding to the public key, and providing the decrypted specific contents to the intended recipient.

    摘要翻译： 使用广播网络向特定收件人传送特定内容的系统和方法。 所述方法包括接收广播节目的AV信号和包含识别特定接收者的标签和特定内容的补充内容。 特定内容使用与特定收件人关联的公钥进行加密。 补充内容与AV信号组合以形成随后用载波信号进行编码和调制的数据增强信号，以形成用于向接收机广播的发送信号。 每个接收机包括用于提取补充内容的补充解码器，用与公开密钥相对应的专用密钥解密特定内容，并将解密的特定内容提供给预期接收者。

    Method and apparatus for pushing a cacheable memory access operation onto a bus controller queue while determining if the cacheable memory access operation hits a cache
    3.
    发明授权
    Method and apparatus for pushing a cacheable memory access operation onto a bus controller queue while determining if the cacheable memory access operation hits a cache 失效
    用于将可缓存存储器访问操作推送到总线控制器队列上同时确定可高速缓存存储器访问操作是否到达高速缓存的方法和装置

    公开(公告)号：US5809550A

    公开(公告)日：1998-09-15

    申请号：US833573

    申请日：1997-04-07

    申请人： Rahul Shukla ,  Jay Heeb ,  Timothy Jehl

    发明人： Rahul Shukla ,  Jay Heeb ,  Timothy Jehl

    IPC分类号： G06F12/08 ,  G06F13/00 ,  G06F12/00

    CPC分类号： G06F12/0804

    摘要： A method and apparatus for hit-dependent flushing of cacheable memory access operations in a bus controller queue is described. The present invention is implemented in the context of a computer system including a microprocessor coupled to an external memory device through an external bus. The processor includes a processor core for issuing memory access operations, a cache, and a bus controller. The bus controller includes a queue having slots for storing pending memory access operations to be sent out over the external bus. After a first memory access operation is issued, the bus controller stores the first memory access operation in a first queue slot before it is determined whether the first operation hits or misses the cache. The bus controller flushes the first operation from the queue if the first operation hits the cache. In response to the processor core issuing a second memory access operation, the bus controller stores the second memory access operation in the first queue slot if the first operation hits the cache. If, on the other hand, the first operation misses the cache, then the bus controller stores the second memory access operation in a second queue slot. Preferably, the first operation is issued in a first cycle and stored in the first queue slot in a second cycle that immediately follows the first cycle, and the second operation is issued in the second cycle.

    摘要翻译： 描述了用于总线控制器队列中的可缓存存储器访问操作的命中相关冲洗的方法和装置。 本发明在包括通过外部总线耦合到外部存储器件的微处理器的计算机系统的上下文中实现。 处理器包括用于发出存储器访问操作的处理器核心，高速缓存和总线控制器。 总线控制器包括具有用于存储要通过外部总线发送出来的未决存储器访问操作的时隙的队列。 在发出第一存储器访问操作之后，总线控制器在确定第一操作是否命中高速缓存之前将第一存储器存取操作存储在第一队列时隙中。 如果第一个操作命中缓存，总线控制器将从队列中刷新第一个操作。 响应于处理器核心发出第二存储器访问操作，如果第一操作命中高速缓存，则总线控制器将第二存储器存取操作存储在第一队列槽中。 另一方面，如果第一操作错过高速缓存，则总线控制器将第二存储器访问操作存储在第二队列时隙中。 优选地，第一操作以第一周期发出，并且在紧接着第一周期的第二周期中被存储在第一队列时隙中，并且在第二周期中发出第二操作。