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    Network performance in virtualized environments
    1.
    发明申请
    Network performance in virtualized environments 审中-公开
    虚拟化环境中的网络性能

    公开(公告)号：US20080005512A1

    公开(公告)日：2008-01-03

    申请号：US11478423

    申请日：2006-06-29

    申请人： Raja Narayanasamy ,  Sujoy Sen ,  Dharmin Y. Parikh

    发明人： Raja Narayanasamy ,  Sujoy Sen ,  Dharmin Y. Parikh

    IPC分类号： G06F12/14 ,  G06F12/00

    CPC分类号： G06F12/126 ,  G06F12/1027 ,  G06F12/1081

    摘要： Methods and apparatus to provide improved network input/output (I/O) performance in virtualized environments are described. In one embodiment, one or more entries of an I/O cache (e.g., a translation lookaside buffer) are locked in response to a request to lock the one or more entries. Other embodiments are also described.

    摘要翻译： 描述了在虚拟化环境中提供改进的网络输入/输出（I / O）性能的方法和装置。 在一个实施例中，响应于锁定一个或多个条目的请求来锁定I / O高速缓存（例如，翻译后备缓冲器）的一个或多个条目。 还描述了其它实施例。

    Memory controller with bank sorting and scheduling
    2.
    发明授权
    Memory controller with bank sorting and scheduling 失效
    内存控制器，具有银行排序和排程

    公开(公告)号：US07698498B2

    公开(公告)日：2010-04-13

    申请号：US11321273

    申请日：2005-12-29

    申请人： Sridhar Lakshmanamurthy ,  Dharmin Y. Parikh ,  Karthik Vaithianathan ,  Gary Lavelle ,  Atul Kwatra

    发明人： Sridhar Lakshmanamurthy ,  Dharmin Y. Parikh ,  Karthik Vaithianathan ,  Gary Lavelle ,  Atul Kwatra

    IPC分类号： G06F12/00 ,  G06F13/14

    CPC分类号： G06F13/28 ,  G06F13/1631 ,  G06F13/1673

    摘要： In some embodiments a memory controller is disclosed that includes at least one command/address input buffer to receive commands and addresses. The addresses specify a memory bank and a location within the memory bank. An arbiter, coupled to the at least one command/address input buffer, merges commands and addresses from the at least one command/address input buffer and sorts the commands and addresses based on the addresses specified. A plurality of bank buffers, coupled to the arbiter and associated with memory banks, receive commands and addresses for their associated memory banks. A scheduler, coupled to the plurality of bank buffers, groups commands and addresses based on an examination of at least one command and address from the bank buffers. Other embodiments are otherwise disclosed herein.

    摘要翻译： 在一些实施例中，公开了一种存储器控制器，其包括用于接收命令和地址的至少一个命令/地址输入缓冲器。 地址指定存储体和存储体内的位置。 耦合到至少一个命令/地址输入缓冲器的仲裁器合并来自至少一个命令/地址输入缓冲器的命令和地址，并根据指定的地址对命令和地址进行排序。 耦合到仲裁器并与存储器组相关联的多个存储体缓冲器接收它们相关存储体的命令和地址。 基于对来自存储体缓冲器的至少一个命令和地址的检查，耦合到多个存储体缓冲器的调度器分组命令和地址。 其他实施例在此另外公开。