公开(公告)号：US06205463B1

公开(公告)日：2001-03-20

申请号：US08850989

申请日：1997-05-05

Applicant: Rajesh Manglore ,  Sudarshan Kumar

Inventor： Rajesh Manglore ,  Sudarshan Kumar

IPC: G06F750

CPC classification number: G06F7/508

Abstract: In one embodiment, an adder is sectioned into a plurality of operational blocks; namely, a first block, second block, and third block. The first block in a first section generates sum bits and a section carry signal. The second block in the second section generates a second plurality of sum bits and a first block carry signal. A third block in the second section receives both the section carry signal and the first block carry signal. The third block includes a carry processor which receives the section carry signal and outputs a second block carry signal corresponding to the third block.

Abstract translation: 在一个实施例中，加法器被分割成多个操作块; 即第一块，第二块和第三块。 第一部分中的第一块产生和位和区段进位信号。 第二部分中的第二块产生第二多个和位和第一块进位信号。 第二部分中的第三块接收片段进位信号和第一块进位信号。 第三块包括进位处理器，其接收段进位信号并输出​​对应于第三块的第二块进位信号。

公开(公告)号：US06201415B1

公开(公告)日：2001-03-13

申请号：US09369079

申请日：1999-08-05

Applicant: Rajesh Manglore

Inventor： Rajesh Manglore

IPC: H03K19096

CPC classification number: H03K19/215 ,  H03K19/0963

Abstract: A time borrowing domino circuit that includes complementary logic outputs and a multiplexor without incurring the time delays normally associated with complementary outputs and multiplexor function is described. A clock delay circuit is described which produces the trailing edge delay clock signal that drives the domino circuit. A domino circuit is described that may implement logical functions such as AND, OR, NAND, NOR, EXCLUSIVE-OR and EXCLUSIVE-NOR. A multiplexor circuit is described for gating one of a number of logical inputs to a latch. And a latch is described having complementary outputs.

Abstract translation: 描述了包括互补逻辑输出和多路复用器的时间借用多米诺骨牌电路，而不会引起通常与互补输出和多路复用器功能相关联的时间延迟。 描述了产生驱动多米诺骨牌电路的后沿延迟时钟信号的时钟延迟电路。 描述可以实现诸如AND，OR，NAND，NOR，EXCLUSIVE-OR和EXCLUSIVE-NOR之类的逻辑功能的多米诺骨牌电路。 描述了多路复用器电路，用于选通锁存器的多个逻辑输入中的一个。 并且描述了具有互补输出的锁存器。

公开(公告)号：US6023767A

公开(公告)日：2000-02-08

申请号：US841839

申请日：1997-05-05

Applicant: Sudarshan Kumar ,  James J. C. Lan ,  Rajesh Manglore

Inventor： Sudarshan Kumar ,  James J. C. Lan ,  Rajesh Manglore

IPC: G06F1/10 ,  G06F1/04

CPC classification number: G06F1/10

Abstract: A method for verifying proper communication between a first circuit and a second circuit of an electronic device. First it is determined which global clocks the first circuit and the second circuit are timed by. Then, the clock signal is shifted between the first and second storage circuits by an amount equal to or greater than a global clock skew budget of the device if it is determined that the first and second storage circuits are timed by different global clocks. Finally, verifying proper operation of the second circuit against a local clock skew budget of the device is done.

Abstract translation: 一种用于验证电子设备的第一电路和第二电路之间的适当通信的方法。 首先确定第一电路和第二电路定时的哪个全局时钟。 然后，如果确定第一和第二存储电路由不同的全局时钟定时，则时钟信号在第一和第二存储电路之间移动等于或大于设备的全局时钟偏差预算的量。 最后，根据设备的本地时钟偏差预算验证第二电路的正确操作。