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公开(公告)号：US11062743B2
公开(公告)日：2021-07-13
申请号：US16802073
申请日：2020-02-26
Applicant: Rambus Inc.
Inventor： Michael L. Takefman , Maher Amer , Claus Reitlingshoefer , Riccardo Badalone
Abstract: A system and method for providing a configurable timing control of a memory system is provided. One system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has flip-flops, a multiplexer coupled to the flip-flops, a first control block for controlling to hold an input data within the flip-flops, and a second control block for controlling a timing of an output data from the flip-flops via the multiplexer with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface.
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公开(公告)号：US11640836B2
公开(公告)日：2023-05-02
申请号：US17372100
申请日：2021-07-09
Applicant: Rambus Inc.
Inventor： Michael L. Takefman , Maher Amer , Claus Reitlingshoefer , Riccardo Badalone
Abstract: A system and method are directed to providing a configurable timing control of a memory system. In one embodiment, the system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has a plurality of flip-flops, a multiplexor coupled to the plurality of flip-flops, a first control block for controlling to hold an input data within the plurality of flipflops, and a second control block for controlling a timing of an output data from the plurality of flip-flops via the multiplexor with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface.
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公开(公告)号：US10580465B2
公开(公告)日：2020-03-03
申请号：US15907390
申请日：2018-02-28
Applicant: Rambus Inc.
Inventor： Michael L. Takefman , Maher Amer , Claus Reitlingshoefer , Riccardo Badalone
Abstract: A system and method for providing a configurable timing control of a memory system is disclosed. In one embodiment, the system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has a plurality of flip-flops, a multiplexor coupled to the plurality of flip-flops, a first control block for controlling to hold an input data within the plurality of flip-flops, and a second control block for controlling a timing of an output data from the plurality of flip-flops via the multiplexor with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface.
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公开(公告)号：US20210407561A1
公开(公告)日：2021-12-30
申请号：US17372100
申请日：2021-07-09
Applicant: Rambus Inc.
Inventor： Michael L. Takefman , Maher Amer , Claus Reitlingshoefer , Riccardo Badalone
Abstract: A system and method for providing a configurable timing control of a memory system is disclosed. In one embodiment, the system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has a plurality of flip-flops, a multiplexor coupled to the plurality of flip-flops, a first control block for controlling to hold an input data within the plurality of flip-flops, and a second control block for controlling a timing of an output data from the plurality of flip-flops via the multiplexor with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface.
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