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    System and method for providing a configurable timing control for a memory system
    3.
    发明授权
    System and method for providing a configurable timing control for a memory system 有权

    公开(公告)号：US11062743B2

    公开(公告)日：2021-07-13

    申请号：US16802073

    申请日：2020-02-26

    Applicant: Rambus Inc.

    Inventor： Michael L. Takefman ,  Maher Amer ,  Claus Reitlingshoefer ,  Riccardo Badalone

    IPC: G11C7/00 ,  G11C7/10 ,  G11C5/04

    Abstract: A system and method for providing a configurable timing control of a memory system is provided. One system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has flip-flops, a multiplexer coupled to the flip-flops, a first control block for controlling to hold an input data within the flip-flops, and a second control block for controlling a timing of an output data from the flip-flops via the multiplexer with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface.

    SYSTEM AND METHOD FOR IMPLEMENTING A MULTI-THREADED DEVICE DRIVER IN A COMPUTER SYSTEM
    4.
    发明申请
    SYSTEM AND METHOD FOR IMPLEMENTING A MULTI-THREADED DEVICE DRIVER IN A COMPUTER SYSTEM 审中-公开

    公开(公告)号：US20190065420A1

    公开(公告)日：2019-02-28

    申请号：US16032241

    申请日：2018-07-11

    Applicant: Rambus Inc.

    Inventor： Bart Trojanowski ,  Michael L. Takefman ,  Maher Amer

    IPC: G06F13/362 ,  G06F9/50 ,  G06F9/30 ,  G06F13/42 ,  G06F13/366

    Abstract: A polling device driver is partitioned into a plurality of driver threads for controlling a device of a computer system. The device has a first device state of an unscouted state and a scouted state, and a second device state of an inactive state and an active state. A driver thread of the plurality of driver threads determines that the first device state of the device state is in the unscouted state, and changes the first state of the device to the scouted state. The driver thread further determines that the second device state of the device is in the inactive state and changes the second device state of the device to the active state. The driver thread executes an operation on the device during a pre-determined time slot configured for the driver thread.

    System and method for providing a configurable timing control for a memory system
    5.
    发明授权
    System and method for providing a configurable timing control for a memory system 有权

    公开(公告)号：US11640836B2

    公开(公告)日：2023-05-02

    申请号：US17372100

    申请日：2021-07-09

    Applicant: Rambus Inc.

    Inventor： Michael L. Takefman ,  Maher Amer ,  Claus Reitlingshoefer ,  Riccardo Badalone

    IPC: G06F13/00 ,  G11C7/10 ,  G11C5/04

    Abstract: A system and method are directed to providing a configurable timing control of a memory system. In one embodiment, the system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has a plurality of flip-flops, a multiplexor coupled to the plurality of flip-flops, a first control block for controlling to hold an input data within the plurality of flipflops, and a second control block for controlling a timing of an output data from the plurality of flip-flops via the multiplexor with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface.

    SYSTEM AND METHOD FOR PROVIDING A CONFIGURABLE TIMING CONTROL FOR A MEMORY SYSTEM
    9.
    发明申请
    SYSTEM AND METHOD FOR PROVIDING A CONFIGURABLE TIMING CONTROL FOR A MEMORY SYSTEM 有权

    公开(公告)号：US20210407561A1

    公开(公告)日：2021-12-30

    申请号：US17372100

    申请日：2021-07-09

    Applicant: Rambus Inc.

    Inventor： Michael L. Takefman ,  Maher Amer ,  Claus Reitlingshoefer ,  Riccardo Badalone

    IPC: G11C7/10 ,  G11C5/04

    Abstract: A system and method for providing a configurable timing control of a memory system is disclosed. In one embodiment, the system has a first interface to receive a DIMM clock and configuration information, a second interface to a first data bus, and a third interface to a second data bus. The system further has a plurality of flip-flops, a multiplexor coupled to the plurality of flip-flops, a first control block for controlling to hold an input data within the plurality of flip-flops, and a second control block for controlling a timing of an output data from the plurality of flip-flops via the multiplexor with a programmable delay. The input data is received via the second interface. The programmable delay is received via the first interface. The output data is sent out with the timing delay via the third interface.

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