公开(公告)号：US20140140389A1

公开(公告)日：2014-05-22

申请号：US14073003

申请日：2013-11-06

Applicant: Rambus Inc.

Inventor： E-Hung Chen

IPC: H04L25/03 ,  H04B1/16

CPC classification number: H04L25/4917 ,  H04L25/03146

Abstract: An integrated circuit is disclosed that includes a receiver circuit to receive duobinary data symbols from a first signaling lane. The receiver circuit includes sampling circuitry to determine symbol state, and a duobinary decoder. The duobinary decoder is coupled to the sampling circuitry and converts the detected states to a PAM2 coded symbol stream. A decision-feedback equalizer (DFE) is provided that has inputs coupled to the sampling circuitry in parallel with the duobinary decoder. The DFE cooperates with the sampling circuitry to form a feedback path, such that the duobinary decoder is external to the feedback path.

Abstract translation: 公开了一种集成电路，其包括从第一信令通道接收双二进制数据符号的接收器电路。 接收机电路包括用于确定符号状态的采样电路和双二进制解码器。 二进制解码器耦合到采样电路，并将检测到的状态转换为PAM2编码符号流。 提供了一个判决反馈均衡器（DFE），其具有与二进制解码器并行地耦合到采样电路的输入。 DFE与采样电路协作以形成反馈路径，使得双二进制解码器在反馈路径的外部。

公开(公告)号：US20160087821A1

公开(公告)日：2016-03-24

申请号：US14860544

申请日：2015-09-21

Applicant: Rambus Inc.

Inventor： E-Hung Chen

IPC: H04L25/49 ,  H04L25/03

CPC classification number: H04L25/4917 ,  H04L25/03146

Abstract: An integrated circuit is disclosed that includes a receiver circuit to receive duobinary data symbols from a first signaling lane. The receiver circuit includes sampling circuitry to determine symbol state, and a duobinary decoder. The duobinary decoder is coupled to the sampling circuitry and converts the detected states to a PAM2 coded symbol stream. A decision-feedback equalizer (DFE) is provided that has inputs coupled to the sampling circuitry in parallel with the duobinary decoder. The DFE cooperates with the sampling circuitry to form a feedback path, such that the duobinary decoder is external to the feedback path.

Abstract translation: 公开了一种集成电路，其包括从第一信令通道接收双二进制数据符号的接收器电路。 接收机电路包括用于确定符号状态的采样电路和双二进制解码器。 二进制解码器耦合到采样电路，并将检测到的状态转换为PAM2编码符号流。 提供了一个判决反馈均衡器（DFE），其具有与二进制解码器并行地耦合到采样电路的输入。 DFE与采样电路协作以形成反馈路径，使得双二进制解码器在反馈路径的外部。

公开(公告)号：US09929883B2

公开(公告)日：2018-03-27

申请号：US14860544

申请日：2015-09-21

Applicant: Rambus Inc.

Inventor： E-Hung Chen

IPC: H04L25/03 ,  H04L25/49

CPC classification number: H04L25/4917 ,  H04L25/03146

Abstract: An integrated circuit is disclosed that includes a receiver circuit to receive duobinary data symbols from a first signaling lane. The receiver circuit includes sampling circuitry to determine symbol state, and a duobinary decoder. The duobinary decoder is coupled to the sampling circuitry and converts the detected states to a PAM2 coded symbol stream. A decision-feedback equalizer (DFE) is provided that has inputs coupled to the sampling circuitry in parallel with the duobinary decoder. The DFE cooperates with the sampling circuitry to form a feedback path, such that the duobinary decoder is external to the feedback path.

公开(公告)号：US09166844B2

公开(公告)日：2015-10-20

申请号：US14073003

申请日：2013-11-06

Applicant: Rambus Inc.

Inventor： E-Hung Chen

IPC: H04L25/03 ,  H04L25/49

CPC classification number: H04L25/4917 ,  H04L25/03146

Abstract: An integrated circuit is disclosed that includes a receiver circuit to receive duobinary data symbols from a first signaling lane. The receiver circuit includes sampling circuitry to determine symbol state, and a duobinary decoder. The duobinary decoder is coupled to the sampling circuitry and converts the detected states to a PAM2 coded symbol stream. A decision-feedback equalizer (DFE) is provided that has inputs coupled to the sampling circuitry in parallel with the duobinary decoder. The DFE cooperates with the sampling circuitry to form a feedback path, such that the duobinary decoder is external to the feedback path.

Abstract translation: 公开了一种集成电路，其包括从第一信令通道接收双二进制数据符号的接收器电路。 接收机电路包括用于确定符号状态的采样电路和双二进制解码器。 二进制解码器耦合到采样电路，并将检测到的状态转换为PAM2编码符号流。 提供了一个判决反馈均衡器（DFE），其具有与二进制解码器并行地耦合到采样电路的输入。 DFE与采样电路协作以形成反馈路径，使得双二进制解码器在反馈路径的外部。