公开(公告)号：US09571077B1

公开(公告)日：2017-02-14

申请号：US14798340

申请日：2015-07-13

Applicant: Rambus Inc.

Inventor： Cosmin Iorga ,  James L. Gorecki

IPC: H03H11/16 ,  H03K5/13 ,  H03K5/135 ,  H03L7/189 ,  H03L7/191

CPC classification number: H03K5/131 ,  H03K5/135

Abstract: A method and device for dynamically updating a phase interpolator circuit module using a phase update circuit module. The method can include interpolating a set of input clock phases based on a phase interpolator code input and sequentially updating the rising edge generator and falling edge generator starting from a synchronizer update signal. The dynamic sequential update involves disabling a rising edge ramp signal while updating a rising edge interpolator and generating old clock out falling edge according to an old phase interpolator code input, disabling a falling edge ramp signal while updating a falling edge interpolator, enabling the rising edge ramp signal and generating a new clock out rising edge according to a new phase interpolator code input, and enabling the falling edge ramp signal and generating a new clock out falling edge according to the new phase interpolator code input.

Abstract translation: 一种使用相位更新电路模块动态更新相位插值器电路模块的方法和装置。 该方法可以包括基于相位内插器代码输入来内插一组输入时钟相位，并且从同步器更新信号开始顺序更新上升沿发生器和下降沿发生器。 动态顺序更新包括在更新上升沿内插器时禁止上升沿斜坡信号，并根据旧相位内插器代码输入产生旧时钟下降沿，在更新下降沿内插器时禁止下降沿斜坡信号，使上升沿 根据新的相位内插器代码输入，产生新的时钟输出上升沿，并根据新的相位内插器代码输入使能下降沿斜坡信号并产生新的时钟下降沿。