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公开(公告)号：US09564909B1
公开(公告)日：2017-02-07
申请号：US14861079
申请日：2015-09-22
Applicant: Rambus Inc.
Inventor： Cosmin Iorga , Sriram Narayan
CPC classification number: H03L7/0818
Abstract: A delay circuit device configured for delay adjustment monotonicity and method of operating therefor. This delay circuit device is configured with hybrid coarse-fine delay cells and uses a sequence of these delay cells activated in a way that builds-up the delay as a sequence of fine steps until it reaches the coarse delay value. This configuration allows for the continuing build of propagation delay by adding the fine steps of the following delay cells. In this manner, the monotonicity of the signal delay circuit is ensured by the architecture independent from device mismatch, thus eliminating problems with conventional delay circuits such as gaps and overlaps specific the these conventional delay cells.
Abstract translation: 延迟电路装置，被配置为延迟调整单调性及其操作方法。 该延迟电路装置配置有混合粗细延迟单元，并且使用以这种方式将这些延迟单元激活的序列作为精细步骤的序列直到达到粗延迟值。 该配置允许通过添加以下延迟单元的精细步骤来继续构建传播延迟。 以这种方式，信号延迟电路的单调性通过独立于器件失配的架构来确保，从而消除了常规延迟电路（例如这些常规延迟单元特有的间隙和重叠）的问题。
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公开(公告)号：US12166485B2
公开(公告)日：2024-12-10
申请号：US17898800
申请日：2022-08-30
Applicant: Rambus Inc.
Inventor： Cosmin Iorga
IPC: H03L7/00 , G11C7/22 , H03K3/0232 , H03K19/17784 , H03L7/081 , H03L7/099 , H03L7/195
Abstract: Described is an integrated circuit with a driving amplifier that transmits a signal over a link (e.g. a wire) by raising and lowering a voltage on the link. A reference oscillator provides an error measure for the rate at which the voltage transitions between voltages, the slew rate. Slew-rate calibration circuitry adjusts the driving amplifier responsive to the error measure.
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公开(公告)号：US20240243662A1
公开(公告)日：2024-07-18
申请号：US18412966
申请日：2024-01-15
Applicant: Rambus Inc.
Inventor： Cosmin Iorga , Panduka Wijetunga
CPC classification number: H02M3/157 , H02M1/0019 , H02M1/0025 , H02M1/0064
Abstract: A DC-DC converter is disclosed. The DC-DC converter includes a sensing circuit having a first path to sense an output current of the DC/DC converter. A reference circuit generates a reference current to flow along a second path. The reference current is for comparison to the output current. A noise injection circuit couples to the second path and includes a replica circuit of the sensing circuit to sense the reference current. A differential amplifier rejects a common mode noise between the first path and the second path.
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4.发明授权公开(公告)号：US09571077B1
公开(公告)日：2017-02-14
申请号：US14798340
申请日：2015-07-13
Applicant: Rambus Inc.
Inventor： Cosmin Iorga , James L. Gorecki
Abstract: A method and device for dynamically updating a phase interpolator circuit module using a phase update circuit module. The method can include interpolating a set of input clock phases based on a phase interpolator code input and sequentially updating the rising edge generator and falling edge generator starting from a synchronizer update signal. The dynamic sequential update involves disabling a rising edge ramp signal while updating a rising edge interpolator and generating old clock out falling edge according to an old phase interpolator code input, disabling a falling edge ramp signal while updating a falling edge interpolator, enabling the rising edge ramp signal and generating a new clock out rising edge according to a new phase interpolator code input, and enabling the falling edge ramp signal and generating a new clock out falling edge according to the new phase interpolator code input.
Abstract translation: 一种使用相位更新电路模块动态更新相位插值器电路模块的方法和装置。 该方法可以包括基于相位内插器代码输入来内插一组输入时钟相位，并且从同步器更新信号开始顺序更新上升沿发生器和下降沿发生器。 动态顺序更新包括在更新上升沿内插器时禁止上升沿斜坡信号，并根据旧相位内插器代码输入产生旧时钟下降沿，在更新下降沿内插器时禁止下降沿斜坡信号，使上升沿 根据新的相位内插器代码输入，产生新的时钟输出上升沿，并根据新的相位内插器代码输入使能下降沿斜坡信号并产生新的时钟下降沿。
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公开(公告)号：US20250141434A1
公开(公告)日：2025-05-01
申请号：US18939768
申请日：2024-11-07
Applicant: Rambus Inc.
Inventor： Cosmin Iorga
IPC: H03K3/0232 , G11C7/22 , H03K19/17784 , H03L7/081 , H03L7/099 , H03L7/195
Abstract: Described is an integrated circuit with a driving amplifier that transmits a signal over a link (e.g. a wire) by raising and lowering a voltage on the link. A reference oscillator provides an error measure for the rate at which the voltage transitions between voltages, the slew rate. Slew-rate calibration circuitry adjusts the driving amplifier responsive to the error measure.
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Patent Agency Ranking
6.发明授权公开(公告)号：US11782476B2
公开(公告)日：2023-10-10
申请号：US17529515
申请日：2021-11-18
Applicant: Rambus Inc.
Inventor： Panduka Wijetunga , Marcial Chua , Srinivas Satish Babu Bamdhamravuri , Abhishek Desai , Philip Lu , Cosmin Iorga
IPC: G06F1/10
CPC classification number: G06F1/10
Abstract: A memory controller conveys a clock signal with command and address signals to a registered clock driver (RCD) on a memory module. A controller-side chip interface on the RCD supports both source-synchronous and filtered clocking for receipt of the command and address signals, the selection between the two clocking schemes dependent upon the noise environment impacting the clock and command/address signals. If the noise is predominantly correlated, then the chip interface is placed in a source-synchronous clocking mode. If the noise is predominantly uncorrelated, then the chip interface is placed in a filtered clocking mode that filters out uncorrelated noise from the clock signal.
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公开(公告)号：US20230080033A1
公开(公告)日：2023-03-16
申请号：US17898800
申请日：2022-08-30
Applicant: Rambus Inc.
Inventor： Cosmin Iorga
IPC: H03K3/0232 , H03K19/17784 , H03L7/099 , H03L7/195 , H03L7/081
Abstract: Described is an integrated circuit with a driving amplifier that transmits a signal over a link (e.g. a wire) by raising and lowering a voltage on the link. A reference oscillator provides an error measure for the rate at which the voltage transitions between voltages, the slew rate. Slew-rate calibration circuitry adjusts the driving amplifier responsive to the error measure.
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8.发明申请公开(公告)号：US20220179444A1
公开(公告)日：2022-06-09
申请号：US17529515
申请日：2021-11-18
Applicant: Rambus Inc.
Inventor： Panduka Wijetunga , Marcial Chua , Srinivas Satish Babu Bamdhamravuri , Abhishek Desai , Philip Lu , Cosmin Iorga
IPC: G06F1/10
Abstract: A memory controller conveys a clock signal with command and address signals to a registered clock driver (RCD) on a memory module. A controller-side chip interface on the RCD supports both source-synchronous and filtered clocking for receipt of the command and address signals, the selection between the two clocking schemes dependent upon the noise environment impacting the clock and command/address signals. If the noise is predominantly correlated, then the chip interface is placed in a source-synchronous clocking mode. If the noise is predominantly uncorrelated, then the chip interface is placed in a filtered clocking mode that filters out uncorrelated noise from the clock signal.
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9.发明授权Phase interpolator device using dynamic stop and phase code update and method therefor 有权使用动态停止和相位代码更新的相位插值器器件及其方法公开(公告)号：US09537475B1
公开(公告)日：2017-01-03
申请号：US14989323
申请日：2016-01-06
Applicant: Rambus Inc.
Inventor： Cosmin Iorga
CPC classification number: H03K5/13 , H03K5/135 , H03K2005/00052 , H03K2005/00286
Abstract: A method and device for dynamically updating a phase interpolator circuit module using an update control circuit module. The method can include providing the phase interpolator with a set of input clock phases to produce a clock signal. The update control module can generate a blanking signal in response to an update signal and apply an update process that stops an old clock output signal after a last clock pulse. The update control module can then update phase select multiplexers for a rising edge integrator and falling edge integrator according to a new phase interpolator code. The update control module can determine a phase jump code and then release the blanking signal during a discharge time interval of the rising edge integrator following a phase jump duration according to the phase jump code. Afterwards, the phase interpolator module can generate the new clock output signal without producing glitches.
Abstract translation: 一种使用更新控制电路模块动态更新相位插值器电路模块的方法和装置。 该方法可以包括为相位插值器提供一组输入时钟相位以产生时钟信号。 更新控制模块可以响应于更新信号产生消隐信号，并应用在最后时钟脉冲之后停止旧时钟输出信号的更新处理。 然后，更新控制模块可以根据新的相位内插器代码来更新上升沿积分器和下降沿积分器的相位选择多路复用器。 更新控制模块可以确定相位跳变码，然后根据相位跳转码在相位跳变持续时间之后的上升沿积分器的放电时间间隔期间释放消隐信号。 之后，相位插值器模块可以产生新的时钟输出信号，而不会产生毛刺。
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公开(公告)号：US12301193B2
公开(公告)日：2025-05-13
申请号：US18236857
申请日：2023-08-22
Applicant: Rambus Inc.
Inventor： Cosmin Iorga , Ruibing Zhang
IPC: H03H11/04
Abstract: A pulse filter circuit is configured to eliminate pulses that are less than a specified duration and pass those that are greater than the specified duration. A buffer receives a signal and applies the buffered signal to a resistance-capacitance charging-discharging circuit (e.g., RC filter). When the output of the RC filter has, in response to the buffered signal, charged or discharged, as appropriate, to cause the output of a slicer to change, logic circuitry controls switching circuitry to pull the output of the RC filter to be fully charged or discharged, respectively. In this manner, pulses that are too short to charge/discharge the RC filter enough to cross the threshold of the slicer do not reach the slicer circuit output, but pulses that are long enough to cross the slicer threshold are transmitted by the slicer.
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