公开(公告)号：US20210004515A1

公开(公告)日：2021-01-07

申请号：US16905724

申请日：2020-06-18

Applicant: Rambus Inc.

Inventor： Lap Wai Chow ,  Bryan J. Wang ,  James P. Baukus ,  Ronald P. Cocchi

IPC: G06F30/392 ,  H01L27/02 ,  G06F21/14 ,  H03K19/17736 ,  H01L27/118 ,  G06F30/39 ,  G06F30/394

Abstract: The camouflage technique described herein introduces programmed configuration inputs to Micro Netlists, creating Programmable Micro Netlists (PMNLs). PMNLs are a group of camouflaged and non-camouflaged cells that may be configured to perform one of several possible logic functions. They retain all the protective properties of non-programmable MNLs, but also allow for secure post-manufacture configuration of their aggregate logic function.

公开(公告)号：US20200295763A1

公开(公告)日：2020-09-17

申请号：US16775077

申请日：2020-01-28

Applicant: Rambus Inc.

Inventor： Ronald P. Cocchi ,  Lap Wai Chow ,  James P. Baukus ,  Bryan J. Wang

IPC: H03K19/17736 ,  G06F21/14 ,  H01L27/02 ,  H03K19/17768 ,  G06F30/39

Abstract: An application specific integrated circuit (ASIC) and a method for its design and fabrication is disclosed. In one embodiment, the camouflaged application specific integrated circuit (ASIC), comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the functional logic cells comprise a camouflage cell including: a source region of a first conductivity type, a drain region of the first conductivity type, and a camouflage region of a second conductivity type disposed between the source region and the drain region. The camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration.

公开(公告)号：US11163930B2

公开(公告)日：2021-11-02

申请号：US16905724

申请日：2020-06-18

Applicant: Rambus Inc.

Inventor： Lap Wai Chow ,  Bryan J. Wang ,  James P. Baukus ,  Ronald P. Cocchi

IPC: G06F21/14 ,  G06F30/392 ,  H01L27/02 ,  H03K19/17736 ,  H01L27/118 ,  G06F30/39 ,  G06F30/394 ,  G06F30/34

Abstract: The camouflage technique described herein introduces programmed configuration inputs to Micro Netlists, creating Programmable Micro Netlists (PMNLs). PMNLs are a group of camouflaged and non-camouflaged cells that may be configured to perform one of several possible logic functions. They retain all the protective properties of non-programmable MNLs, but also allow for secure post-manufacture configuration of their aggregate logic function.

公开(公告)号：US20210249364A1

公开(公告)日：2021-08-12

申请号：US17157579

申请日：2021-01-25

Applicant: Rambus Inc.

Inventor： Lap Wai Chow ,  Bryan J. Wang ,  James P. Baukus ,  Ronald P. Cocchi

IPC: H01L23/00 ,  H01L29/10 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/78

Abstract: A camouflaged application specific integrated circuit is disclosed. The camouflaged ASIC includes at least one camouflaged FinFET, which includes a substrate of a first conductivity type, a fin, disposed on the substrate, the fin including a source region of a second conductivity type, a drain region of the second conductivity type, and a channel region of the first conductivity type. The camouflaged application specific integrated circuit also includes a gate disposed over and substantially perpendicular to the channel region, forming one or more transistor junctions with the fin. In one embodiment, the substrate includes a punch through stop (PTS) region of the second conductivity type disposed between the fin and the substrate, the PTS region electrically shorting the source region of the fin to the drain region of the fin.

公开(公告)号：US11664332B2

公开(公告)日：2023-05-30

申请号：US17157579

申请日：2021-01-25

Applicant: Rambus Inc.

Inventor： Lap Wai Chow ,  Bryan J. Wang ,  James P. Baukus ,  Ronald P. Cocchi

IPC: H01L23/00 ,  H01L29/10 ,  H01L29/78 ,  H01L21/8238 ,  H01L29/66 ,  H01L27/092

CPC classification number: H01L23/576 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/1083 ,  H01L29/66795 ,  H01L29/785

Abstract: A camouflaged application specific integrated circuit is disclosed. The camouflaged ASIC includes at least one camouflaged FinFET, which includes a substrate of a first conductivity type, a fin, disposed on the substrate, the fin including a source region of a second conductivity type, a drain region of the second conductivity type, and a channel region of the first conductivity type. The camouflaged application specific integrated circuit also includes a gate disposed over and substantially perpendicular to the channel region, forming one or more transistor junctions with the fin. In one embodiment, the substrate includes a punch through stop (PTS) region of the second conductivity type disposed between the fin and the substrate, the PTS region electrically shorting the source region of the fin to the drain region of the fin.

公开(公告)号：US11637076B2

公开(公告)日：2023-04-25

申请号：US17157567

申请日：2021-01-25

Applicant: Rambus Inc.

Inventor： Lap Wai Chow ,  Bryan J. Wang ,  James P. Baukus ,  Ronald P. Cocchi

IPC: H01L23/00 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66

Abstract: A system and method for adding a source contact, a drain contact, and an apparent gate contact to a FinFET having a fin including a source region, a drain region, and a gate disposed over the fin forming one or more transistor junctions with the fin. The method comprises producing a source contact opening extending downward to a first region electrically coupled to the source region, a drain contact opening extending downward to a second region electrically coupled to the drain region, and a gate contact opening extending downward to a third region electrically isolated from the gate, and filling the source contact opening, the drain contact opening, and the gate contact opening with a conductive metal.

公开(公告)号：US11264990B2

公开(公告)日：2022-03-01

申请号：US16775077

申请日：2020-01-28

Applicant: Rambus Inc.

Inventor： Ronald P. Cocchi ,  Lap Wai Chow ,  James P. Baukus ,  Bryan J. Wang

IPC: H03K19/17736 ,  G06F21/14 ,  H01L27/02 ,  H03K19/17768 ,  G06F30/39 ,  H01L27/118 ,  G06F30/30 ,  G06F30/392

Abstract: An application specific integrated circuit (ASIC) and a method for its design and fabrication is disclosed. In one embodiment, the camouflaged application specific integrated circuit (ASIC), comprises a plurality of interconnected functional logic cells that together perform one or more ASIC logical functions, wherein the functional logic cells comprise a camouflage cell including: a source region of a first conductivity type, a drain region of the first conductivity type, and a camouflage region of a second conductivity type disposed between the source region and the drain region. The camouflage region renders the camouflage cell always off in a first camouflage cell configuration and always on in a second camouflage cell configuration having a planar layout substantially indistinguishable from the first configuration.

公开(公告)号：US20210249363A1

公开(公告)日：2021-08-12

申请号：US17157567

申请日：2021-01-25

Applicant: Rambus Inc.

Inventor： Lap Wai Chow ,  Bryan J. Wang ,  James P. Baukus ,  Ronald P. Cocchi

IPC: H01L23/00 ,  H01L29/66 ,  H01L29/423 ,  H01L29/417

Abstract: A system and method for adding a source contact, a drain contact, and an apparent gate contact to a FinFET having a fin including a source region, a drain region, and a gate disposed over the fin forming one or more transistor junctions with the fin. The method comprises producing a source contact opening extending downward to a first region electrically coupled to the source region, a drain contact opening extending downward to a second region electrically coupled to the drain region, and a gate contact opening extending downward to a third region electrically isolated from the gate, and filling the source contact opening, the drain contact opening, and the gate contact opening with a conductive metal.