公开(公告)号：US20220319578A1

公开(公告)日：2022-10-06

申请号：US17715370

申请日：2022-04-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Zhichao Lu ,  Kenneth Lee Wright

IPC: G11C11/4091 ,  G06F11/10 ,  G11C11/4076

Abstract: Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.

公开(公告)号：US10762010B2

公开(公告)日：2020-09-01

申请号：US15808595

申请日：2017-11-09

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

IPC: G06F13/00 ,  G06F13/16 ,  G06F13/28

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

公开(公告)号：US20220382691A1

公开(公告)日：2022-12-01

申请号：US17830838

申请日：2022-06-02

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

IPC: G06F13/16 ,  G06F13/28

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

公开(公告)号：US20180166120A1

公开(公告)日：2018-06-14

申请号：US15829787

申请日：2017-12-01

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Zhichao Lu ,  Kenneth Lee Wright

IPC: G11C11/4091 ,  G06F11/10

Abstract: Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.

公开(公告)号：US11309015B2

公开(公告)日：2022-04-19

申请号：US16999869

申请日：2020-08-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Zhichao Lu ,  Kenneth Lee Wright

IPC: G11C11/34 ,  G11C11/4091 ,  G06F11/10 ,  G11C11/4076

Abstract: Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.

公开(公告)号：US20240273039A1

公开(公告)日：2024-08-15

申请号：US18589259

申请日：2024-02-27

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

IPC: G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1673 ,  G06F13/1678 ,  G06F13/28

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

公开(公告)号：US11947474B2

公开(公告)日：2024-04-02

申请号：US17830838

申请日：2022-06-02

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

IPC: G06F13/00 ,  G06F13/16 ,  G06F13/28

CPC classification number: G06F13/1673 ,  G06F13/1678 ,  G06F13/28

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.

公开(公告)号：US11804259B2

公开(公告)日：2023-10-31

申请号：US17715370

申请日：2022-04-07

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Zhichao Lu ,  Kenneth Lee Wright

IPC: G11C11/34 ,  G11C11/4091 ,  G06F11/10 ,  G11C11/4076

CPC classification number: G11C11/4091 ,  G06F11/10 ,  G06F11/1004 ,  G11C11/4076 ,  G11C2207/2263

Abstract: Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.

公开(公告)号：US20210035623A1

公开(公告)日：2021-02-04

申请号：US16999869

申请日：2020-08-21

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Zhichao Lu ,  Kenneth Lee Wright

IPC: G11C11/4091 ,  G06F11/10 ,  G11C11/4076

Abstract: Memory devices, controllers and associated methods are disclosed. In one embodiment, a memory device is disclosed. The memory device includes storage cells that are each formed with a metal-oxide-semiconductor (MOS) transistor having a floating body. Data is stored as charge in the floating body. A transfer interface receives a read command to access data stored in a first group of the storage cells. Sensing circuitry detects the data stored in the first group of storage cells. The transfer interface selectively performs a writeback operation of the sensed data associated with the read command.

公开(公告)号：US20210004337A1

公开(公告)日：2021-01-07

申请号：US16942380

申请日：2020-07-29

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt ,  Kenneth Lee Wright

IPC: G06F13/16 ,  G06F13/28

Abstract: A memory module comprises an address buffer circuit, a command/address channel, and a plurality of memory components controlled by the address buffer circuit via the command/address channel. At least one memory component comprises a plurality of data ports, a memory core to store data, and a data interface. The data interface is capable of transferring data between the memory core and the data ports. The data interface supports a first data width mode in which the data interface transfers data at a first bit width and a first burst length via the data ports. The data interface also supports a second data width mode in which the data interface transfers data at a second bit width and second burst length via the data ports. The first bit width is greater than the second bit width and the first burst length is shorter than the second burst length.