公开(公告)号：US20230376067A1

公开(公告)日：2023-11-23

申请号：US18320384

申请日：2023-05-19

Applicant: Rambus Inc.

Inventor： Robert WANG ,  Zhuobin LI ,  Navid YAGHINI ,  Hemesh YASOTHARAN ,  Clifford TING

IPC: G06F1/12 ,  G06F1/08 ,  G06F1/10

CPC classification number: G06F1/12 ,  G06F1/08 ,  G06F1/10

Abstract: A circuit and method are provided for setting a phase relationship between a first signal and a second signal having a known frequency relationship to a master signal but having an unknown phase relationship to each other. One or more phase signals is generated based on the master signal, the phase signals having different phases from each other. One of these phase signals is selected based on the phase of the first signal and a target phase delay between the first signal and second signal. The second signal is generated based on the phase and frequency of the selected phase signal.

公开(公告)号：US20220166413A1

公开(公告)日：2022-05-26

申请号：US17535776

申请日：2021-11-26

Applicant: Rambus Inc.

Inventor： Clifford TING ,  Hemesh YASOTHARAN ,  Navid YAGHINI ,  Robert WANG ,  Zhuobin LI

IPC: H03K3/037 ,  H03K5/24

Abstract: A circuit and method for storing bit values in capacitors of a set-reset latch of a dynamic comparator are described. A capacitor-based SR latch architecture is disclosed that makes use of the parasitic capacitances present at its output to store a digital bit value. During the comparator's sampling phase, the capacitor-based SR latch behaves as an inverter and buffers the sampled value to the output of the SR latch. In doing so, it charges the parasitic capacitors associated with the routing and downstream circuitry up or down. When the dynamic comparator enters the reset phase, the SR latch turns off and makes use of the of the parasitic capacitors to hold the previously-buffered value.