公开(公告)号：US20150331817A1

公开(公告)日：2015-11-19

申请号：US14408955

申请日：2013-10-14

Applicant: Rambus Inc.

Inventor： Minghui HAN ,  Amir AMIRKHANY ,  Ravindranath KOLLIPARA ,  Ralf Michael SCHMITT

IPC: G06F13/28 ,  G06F3/06

CPC classification number: G06F13/28 ,  G06F3/0611 ,  G06F3/0635 ,  G06F3/0683 ,  G11C5/04 ,  G11C5/063 ,  G11C7/1084

Abstract: A memory system includes a two memory modules and a memory controller. The memory modules each include at least a first memory package corresponding to a first number of memory ranks (e.g. one memory rank) and a second memory package corresponding to a second number of memory ranks (e.g. two memory ranks) that is greater than the first number of memory ranks For each module, the memory packages may be asymmetrically staggered such that one memory package is further from the memory controller than the other memory package. The memory controller is coupled to the memory packages of both modules via a common data line and generates control information for controlling the on-die termination (ODT) of the memory packages.

Abstract translation: 存储器系统包括两个存储器模块和存储器控制器。 所述存储器模块至少包括对应于第一数量的存储器级别（例如一个存储器级别）的第一存储器包和对应于第二数量的存储器级别（例如，两个存储器级别）的第二存储器包，其大于第一存储器级 内存列数对于每个模块，内存包可能是不对称交错的，这样一个内存包比存储器包更远离存储器控制器。 存储器控制器经由公共数据线耦合到两个模块的存储器封装，并且生成用于控制存储器封装的片上端接（ODT）的控制信息。