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公开(公告)号：US20240365528A1
公开(公告)日：2024-10-31
申请号：US18643224
申请日：2024-04-23
发明人： Changhoon SUNG , Hyojin Cho , Hoyoung Tang , Taehyung Kim , Eojin Lee
IPC分类号： H10B10/00 , G11C5/06 , H01L23/528 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/775 , H01L29/78 , H01L29/786
CPC分类号： H10B10/125 , G11C5/063 , H01L23/5283 , H01L27/0924 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/7851 , H01L29/78696
摘要： An integrated circuit is provided and includes a memory cell array, a plurality of gate electrodes extending in a first direction above a substrate, a plurality of word lines extending in the first direction above the substrate, a plurality of bit lines extending below the substrate in a second direction intersecting the first direction, and a plurality of first contacts passing through the substrate in a vertical direction and respectively connected to the plurality of bit lines.
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公开(公告)号：US20240363616A1
公开(公告)日：2024-10-31
申请号：US18769004
申请日：2024-07-10
发明人： Hidehiro FUJIWARA , Sahil Preet SINGH , Chih-Yu LIN , Hsien-Yu PAN , Yen-Huei CHEN , Hung-Jen LIAO
IPC分类号： H01L27/02 , G11C5/06 , G11C7/18 , H01L23/522 , H10B10/00
CPC分类号： H01L27/0207 , G11C5/063 , G11C7/18 , H01L23/5226 , H10B10/12
摘要： A memory array includes a first memory cell configured to store data, a second memory cell configured to store data and a bit line extending along the first direction, and being over the first memory cell and the second memory cell. The first memory cell and the second memory cell are arranged along a first direction in a first column of memory cells. The bit line includes a first conductor extending in the first direction and being in a first conductive layer, and a second conductor extending in the first direction and being in a second conductive layer different from the first conductive layer.
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公开(公告)号：US20240363531A1
公开(公告)日：2024-10-31
申请号：US18626935
申请日：2024-04-04
发明人： Soyeon Kim , Hoyoung Tang , Taehyung Kim
IPC分类号： H01L23/528 , G11C5/06 , G11C11/419 , H01L27/092 , H01L29/06 , H01L29/423 , H01L29/775 , H01L29/78 , H01L29/786 , H10B10/00
CPC分类号： H01L23/5283 , G11C5/063 , G11C11/419 , H01L27/0924 , H01L29/0673 , H01L29/42392 , H01L29/775 , H01L29/7851 , H01L29/78696 , H10B10/125
摘要： Provided is an integrated circuit including a cell array disposed on a substrate and including a plurality of bit cells, a row decoder including a plurality of word line drivers each providing a plurality of word line signals to the cell array, a backside wiring layer disposed on a back side of the substrate to overlap the row decoder and providing power to the plurality of word line drivers, and a plurality of backside contacts between the row decoder and the backside wiring layer. Each of the plurality of backside contacts extends from a source of at least one transistor included in each of the plurality of word line drivers to the backside wiring layer.
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公开(公告)号：US20240363150A1
公开(公告)日：2024-10-31
申请号：US18640422
申请日：2024-04-19
CPC分类号： G11C5/063 , G11C16/0483 , H01L21/0274 , H10B41/10 , H10B41/35 , H10B43/10 , H10B43/35
摘要： Disclosed are approaches for wordline contact formation for 3D NAND devices. Methods may include providing a film stack of alternating first layers and second layers, forming a first lithography mask over the film stack, and performing a first series of alternating lithography and etch processes to form an array of contact opening pairs in the film stack, wherein an opening through the first lithography mask is expanded in a first direction following each etch process, and wherein a depth of the array of contact opening pairs varies in the first direction. The method may further include forming a second lithography mask over the film stack, and performing a second series of alternating lithography and etch processes, wherein an opening through the second lithography mask is expanded in a second direction following each etch process, and wherein the depth of the array of contact opening pairs varies in the second direction.
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5.发明授权公开(公告)号：US12131796B2
公开(公告)日：2024-10-29
申请号：US18195860
申请日：2023-05-10
申请人： Rambus Inc.
发明人： Yohan Frans
IPC分类号： G11C5/02 , G11C5/06 , G11C7/10 , G11C7/22 , H01L25/065
CPC分类号： G11C7/10 , G11C5/02 , G11C5/063 , G11C7/22 , G11C5/025 , H01L25/0657 , H01L2224/16146 , H01L2224/16225 , H01L2224/17181 , H01L2224/4824 , H01L2224/73257 , H01L2225/0651 , H01L2225/06513 , H01L2225/06517 , H01L2225/06565 , H01L2924/15151 , H01L2924/15192 , H01L2924/15311
摘要： A packaged semiconductor device includes a data pin, a first memory die, and a second memory die stacked with the first memory die. The first memory die includes a first data interface coupled to the data pin and a first memory core having a plurality of banks. The second memory die includes a second memory core having a plurality of banks. A respective bank of the first memory core and a respective bank of the second memory core perform parallel row access operations in response to a first command signal and parallel column access operations in response to a second command signal. The first data interface of the first die provides aggregated data from the parallel column access operations in the first and second die to the data pin.
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公开(公告)号：US12131794B2
公开(公告)日：2024-10-29
申请号：US17893681
申请日：2022-08-23
CPC分类号： G11C5/025 , G11C5/063 , G11C8/14 , H10B12/488
摘要： Methods, systems, and devices for structures for word line multiplexing in three-dimensional memory arrays are described. A memory die may include circuitry for access line multiplexing in regions adjacent to or between staircase regions. For example, a multiplexing region may include, for each word line of a stack of word lines, a respective first portion of a semiconductor material and a respective second portion of the semiconductor material, and may also include one or more gate material portions operable to modulate a conductivity between respective first and second portions. Each word line may be coupled with the respective first portion of the semiconductor material, such that biasing of the gate material portions may couple the word lines with the respective second portion of the semiconductor material. Such features may support various techniques for multiplexing associated with the stack of word lines, or among multiple stacks of word lines, or both.
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公开(公告)号：US20240355364A1
公开(公告)日：2024-10-24
申请号：US18763048
申请日：2024-07-03
发明人： Meng-Sheng Chang , Chia-En Huang , Yi-Ching Liu , Yih Wang
IPC分类号： G11C5/06
CPC分类号： G11C5/063
摘要： Disclosed herein are related to a memory array including a set of memory cells and a set of switches to configure the set of memory cells. In one aspect, each switch is connected between a corresponding local line and a corresponding subset of memory cells. The local clines may be connected to a global line. Local lines may be metal rails, for example, local bit lines or local select lines. A global line may be a metal rail, for example, a global bit line or a global select line. A switch may be enabled or disabled to electrically couple a controller to a selected subset of memory cells through the global line. Accordingly, the set of memory cells can be configured through the global line rather than a number of metal rails to achieve area efficiency.
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公开(公告)号：US20240341081A1
公开(公告)日：2024-10-10
申请号：US18388295
申请日：2023-11-09
发明人： Hongjun LEE , Keunnam KIM , Seungmuk KIM , Kiseok LEE
CPC分类号： H10B12/315 , G11C5/063 , H10B12/482 , H10B12/485 , H10B12/488 , H10B12/50
摘要： A semiconductor device which includes a semiconductor substrate having a cell area and a peripheral area, the peripheral area including a first area and a second area adjacent to each other, first transistors on the first area, a first wiring layer on the first transistors, a first pad on the second area and a portion of the first area, a first contact plug between the first wiring layer and the first area, a second contact plug between the first pad and the first area, a second pad on the first wiring layer, a third contact plug between the second pad and the first wiring layer, and a plurality of first capacitors on the second pad and that vertically overlap the first transistors, thus reliability and electrical characteristics of the semiconductor device may be increased.
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公开(公告)号：US20240339135A1
公开(公告)日：2024-10-10
申请号：US18365726
申请日：2023-08-04
申请人： SK hynix Inc.
发明人： Yong Jin JEONG , Sang Gu YEO
CPC分类号： G11C5/063 , H10B63/84 , H10N70/021 , H10N70/841
摘要： A semiconductor device may include a first contact plug, a word line electrically connected to the first contact plug and extending in a first direction, a second contact plug, a bit line extending in a second direction that intersects the first direction, and a memory cell disposed between the word line and the bit line and including a variable resistance layer. The bit line may include a first protruding part that protrudes into the memory cell, a second protruding part that is connected to the second contact plug, and a connection part that connects the first protruding part and the second protruding part and that extends in the second direction.
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公开(公告)号：US12114486B2
公开(公告)日：2024-10-08
申请号：US17370323
申请日：2021-07-08
发明人： Wei Wan
CPC分类号： H10B12/485 , G11C5/063 , H10B12/315 , H10B12/488
摘要： A semiconductor structure and a method for forming the same are provided. The method includes: providing a semiconductor substrate; determining a position of a bit line contact opening on a top surface of the semiconductor substrate and a top surface of a first dielectric layer; etching an active region, the first dielectric layer and an isolation structure exposed by the bit line contact opening according to the position of the bit line contact opening until the active region is etched to a preset depth to form a bit line contact window; and forming a second dielectric layer on a surface of the isolation structure and a surface of the first dielectric layer that have a depth greater than a depth of a surface of the active region in the bit line contact window.
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