公开(公告)号：US10467014B2

公开(公告)日：2019-11-05

申请号：US16026733

申请日：2018-07-03

Applicant: Rambus Inc.

Inventor： William C. Moyer ,  Jeffrey W. Scott

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/10

Abstract: A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.

公开(公告)号：US09135010B2

公开(公告)日：2015-09-15

申请号：US13750345

申请日：2013-01-25

Applicant: Rambus Inc.

Inventor： William C. Moyer ,  Jeffrey W. Scott

IPC: G06F9/38 ,  G06F9/30 ,  G06F11/10

CPC classification number: G06F9/3875 ,  G06F9/3004 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/38 ,  G06F9/3861 ,  G06F9/3867 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1076

Abstract: Systems and methods are disclosed for processing data. In accordance with one implementation, a processor may include an arithmetic logic unit (ALU). The processor may also include pipeline circuitry to, in a non-error correction code (ECC) operating mode, execute a sequence of single-cycle instructions in the ALU in a first execution stage, and in an ECC operating mode, execute the same sequence of single-cycle instructions in the ALU in a second execution stage instead of the first execution stage. Further, the processor may include mode control signaling to configure the pipeline circuitry between the non-ECC and ECC operating modes.

Abstract translation: 公开了用于处理数据的系统和方法。 根据一个实现，处理器可以包括算术逻辑单元（ALU）。 处理器还可以包括流水线电路，以非纠错码（ECC）操作模式，在第一执行阶段中在ALU中执行一个单周期指令序列，并且在ECC操作模式中，执行相同的序列 在第二执行阶段而不是第一执行阶段的ALU中的单循环指令。 此外，处理器可以包括模式控制信令以在非ECC和ECC操作模式之间配置流水线电路。

公开(公告)号：US10019266B2

公开(公告)日：2018-07-10

申请号：US14852200

申请日：2015-09-11

Applicant: Rambus Inc.

Inventor： William C. Moyer ,  Jeffrey W. Scott

IPC: G06F9/30 ,  G06F9/38 ,  G06F11/10

CPC classification number: G06F9/3875 ,  G06F9/3004 ,  G06F9/30181 ,  G06F9/30189 ,  G06F9/38 ,  G06F9/3861 ,  G06F9/3867 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1076

Abstract: A method includes providing a data processor having an instruction pipeline, where the instruction pipeline has a plurality of instruction pipeline stages, and where the plurality of instruction pipeline stages includes a first instruction pipeline stage and a second instruction pipeline stage. The method further includes providing a data processor instruction that causes the data processor to perform a first set of computational operations during execution of the data processor instruction, performing the first set of computational operations in the first instruction pipeline stage if the data processor instruction is being executed and a first mode has been selected, and performing the first set of computational operations in the second instruction pipeline stage if the data processor instruction is being executed and a second mode has been selected.