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公开(公告)号：US07673273B2
公开(公告)日：2010-03-02
申请号：US11712380
申请日：2007-03-01
IPC分类号： G06F17/50
CPC分类号： H03K19/17796
摘要： A smaller mask programmable gate array (MPGA) device derived from a larger field programmable gate array (FPGA), comprising: a layout of transistors and a plurality of interconnect layers substantially identical to a smaller region of the FPGA; and input/output pads matching a subset of the input/output pads of the FPGA; wherein, a design that is mapped to said smaller region of the FPGA device using said subset of input/output pads by a user programmable means can be identically mapped to the MPGA by a hard-wire circuit. Such a gate array further comprises a mask programmable metal-circuit in lieu of a user programmable configuration circuit of the FPGA; and a logic block to input/output pad connection in lieu of a logic block to a register at the boundary of said smaller region to an input/output pad connection of the FPGA.
摘要翻译： 从较大的现场可编程门阵列（FPGA）导出的较小的掩模可编程门阵列（MPGA）器件，包括：晶体管的布局和与FPGA的较小区域基本相同的多个互连层; 以及与FPGA的输入/输出焊盘的子集匹配的输入/输出焊盘; 其中，使用用户可编程装置的所述输入/输出焊盘子集映射到所述FPGA器件的所述较小区域的设计可以通过硬线电路被相同地映射到MPGA。 这种门阵列还包括代替FPGA的用户可编程配置电路的掩模可编程金属电路; 以及逻辑块，以将代替逻辑块的输入/输出焊盘连接输入到所述较小区域的边界处的寄存器到FPGA的输入/输出焊盘连接。
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公开(公告)号：USRE45110E1
公开(公告)日：2014-09-02
申请号：US13411486
申请日：2012-03-02
IPC分类号： G06F17/50
CPC分类号： G06F17/5054 , G06F17/5045 , G11C16/0433 , G11C17/16 , H01L27/1052 , H03K19/17796
摘要： A smaller mask programmable gate array (MPGA) device derived from a larger field programmable gate array (FPGA), comprising: a layout of transistors and a plurality of interconnect layers substantially identical to a smaller region of the FPGA; and input/output pads matching a subset of the input/output pads of the FPGA; wherein, a design that is mapped to said smaller region of the FPGA device using said subset of input/output pads by a user programmable means can be identically mapped to the MPGA by a hard-wire circuit. Such a gate array further comprises a mask programmable metal-circuit in lieu of a user programmable configuration circuit of the FPGA; and a logic block to input/output pad connection in lieu of a logic block to a register at the boundary of said smaller region to an input/output pad connection of the FPGA.
摘要翻译： 从较大的现场可编程门阵列（FPGA）导出的较小的掩模可编程门阵列（MPGA）器件，包括：晶体管的布局和与FPGA的较小区域基本相同的多个互连层; 以及与FPGA的输入/输出焊盘的子集匹配的输入/输出焊盘; 其中，使用用户可编程装置的所述输入/输出焊盘子集映射到所述FPGA器件的所述较小区域的设计可以通过硬线电路被相同地映射到MPGA。 这种门阵列还包括代替FPGA的用户可编程配置电路的掩模可编程金属电路; 以及逻辑块，以将代替逻辑块的输入/输出焊盘连接输入到所述较小区域的边界处的寄存器到FPGA的输入/输出焊盘连接。
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公开(公告)号：US20080024165A1
公开(公告)日：2008-01-31
申请号：US11494001
申请日：2006-07-28
IPC分类号： H03K19/177
CPC分类号： H03K19/1776 , H03K19/17736 , H03K19/1778
摘要： Programmable routing structures to couple physical memory nodes to logical memory nodes in embedded multi-port memory FPGA's are disclosed. In a first embodiment, a plurality of physical domain nodes couples a plurality of variable node sets in a logical read domain, wherein a configuration element activates one of the sets and selects a fixed input or an address signal to decode the data read. In a second embodiment, a plurality of physical domain nodes couples a plurality of variable node sets in a logical write domain, wherein a configuration element activates one of the sets and couples a fixed input or an address signal to an enable signal of a driver device to decode the data written. A third embodiment provide logical read and logical write functions for a single port in a multi-port physical memory array, wherein the logical read data width and the logical write data width can be independently configured, and wherein the read and write functions share common address lines.
摘要翻译： 公开了将物理存储器节点耦合到嵌入式多端口存储器中的逻辑存储器节点的可编程路由结构。 在第一实施例中，多个物理域节点将逻辑读取域中的多个可变节点集耦合，其中配置元素激活该组中的一个，并选择固定输入或地址信号来解码读取的数据。 在第二实施例中，多个物理域节点将逻辑写入域中的多个可变节点集耦合，其中配置元件激活该组中的一个，并将固定输入或地址信号耦合到驱动器设备的使能信号 解码写入的数据。 第三实施例为多端口物理存储器阵列中的单个端口提供逻辑读取和逻辑写入功能，其中可以独立地配置逻辑读取数据宽度和逻辑写入数据宽度，并且其中读取和写入功能共享公共地址 线条。
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公开(公告)号：US07716622B2
公开(公告)日：2010-05-11
申请号：US11767385
申请日：2007-06-22
CPC分类号： G06F17/5054
摘要： Memory modules implemented on an FPGA device are re-implemented to improve the performance of the device, such as to reduce logic delays. One or more logic blocks of the FPGA device that realize the logic function of a memory module or portion of a memory module are desirably selected. Based on the outcome of a timing analysis, the most critical signal pin of the selected logic blocks may be identified. Methods of deriving the memory module re-implementation for various types of the most critical pins are disclosed. Procedures are described for integrating physical timing analysis, memory transformation, placement, and routing, as well as for the selection of logic blocks for re-implementation.
摘要翻译： 重新实现在FPGA器件上实现的存储器模块以改善器件的性能，例如减少逻辑延迟。 期望选择实现存储器模块或存储器模块的一部分的逻辑功能的FPGA器件的一个或多个逻辑块。 基于定时分析的结果，可以识别所选逻辑块的最关键的信号引脚。 公开了为各种类型的最关键的引脚导出存储器模块重新实现的方法。 描述了用于集成物理时序分析，存储器转换，布局和路由以及用于重新实现的逻辑块的选择的过程。
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公开(公告)号：US07251803B2
公开(公告)日：2007-07-31
申请号：US10785608
申请日：2004-02-23
IPC分类号： G06F17/50
CPC分类号： G06F17/5054
摘要： Memory modules implemented on an FPGA device are re-implemented to improve the performance of the device, such as to reduce logic delays. One or more logic blocks of the FPGA device that realize the logic function of a memory module or portion of a memory module are desirably selected. Based on the outcome of a timing analysis, the most critical signal pin of the selected logic blocks may be identified. Methods of deriving the memory module re-implementation for various types of the most critical pins are disclosed. Procedures are described for integrating physical timing analysis, memory transformation, placement, and routing, as well as for the selection of logic blocks for re-implementation.
摘要翻译： 重新实现在FPGA器件上实现的存储器模块以改善器件的性能，例如减少逻辑延迟。 期望选择实现存储器模块或存储器模块的一部分的逻辑功能的FPGA器件的一个或多个逻辑块。 基于定时分析的结果，可以识别所选逻辑块的最关键的信号引脚。 公开了为各种类型的最关键的引脚导出存储器模块重新实现的方法。 描述了用于集成物理时序分析，存储器转换，布局和路由以及用于重新实现的逻辑块的选择的过程。
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