公开(公告)号：US07474576B2

公开(公告)日：2009-01-06

申请号：US12053261

申请日：2008-03-21

申请人： Ramon S. Co ,  David Sun

发明人： Ramon S. Co ,  David Sun

IPC分类号： G11C29/00

CPC分类号： G11C5/04 ,  G11C29/808 ,  G11C29/88

摘要： A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module. The AMB fully buffers memory requests that are sent as serial packets over southbound lanes from a host. Memory-access addresses are extracted from the serial packets by the AMB. The repair controller compares the memory-access addresses to repair addresses and diverts access from defective memory chips to a spare memory for the repair addresses. The repair addresses can be located during testing of the memory module and programmed into a repair address buffer on the AMB. The repair addresses could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to the repair address buffer on the AMB during power-up.

摘要翻译： 修复全缓冲存储器模块可以具有存在诸如单位错误等缺陷的存储器芯片。 修复控制器被添加到内存模块的高级内存缓冲区（AMB）中。 AMB完全缓冲从主机通过南行车道作为串行数据包发送的内存请求。 AMB从串行数据包中提取存储器访问地址。 修复控制器将存储器访问地址与修复地址进行比较，并将从缺陷存储器芯片的访问转移到用于修复地址的备用存储器。 修复地址可以在测试存储器模块期间定位并编程到AMB上的修复地址缓冲区中。 修复地址可以首先编程到存储器模块上的串行存在检测电可擦除可编程只读存储器（SPD-EEPROM）中，然后在上电期间复制到AMB上的修复地址缓冲区。

公开(公告)号：US20080165600A1

公开(公告)日：2008-07-10

申请号：US12053261

申请日：2008-03-21

申请人： Ramon S. Co ,  David Sun

发明人： Ramon S. Co ,  David Sun

IPC分类号： G11C29/00 ,  G11C8/00

CPC分类号： G11C5/04 ,  G11C29/808 ,  G11C29/88

摘要： A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module. The AMB fully buffers memory requests that are sent as serial packets over southbound lanes from a host. Memory-access addresses are extracted from the serial packets by the AMB. The repair controller compares the memory-access addresses to repair addresses and diverts access from defective memory chips to a spare memory for the repair addresses. The repair addresses can be located during testing of the memory module and programmed into a repair address buffer on the AMB. The repair addresses could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to the repair address buffer on the AMB during power-up.

摘要翻译： 修复全缓冲存储器模块可以具有存在诸如单位错误等缺陷的存储器芯片。 修复控制器被添加到内存模块的高级内存缓冲区（AMB）中。 AMB完全缓冲从主机通过南行车道作为串行数据包发送的内存请求。 AMB从串行数据包中提取存储器访问地址。 修复控制器将存储器访问地址与修复地址进行比较，并将从缺陷存储器芯片的访问转移到用于修复地址的备用存储器。 修复地址可以在测试存储器模块期间定位并编程到AMB上的修复地址缓冲区中。 修复地址可以首先编程到存储器模块上的串行存在检测电可擦除可编程只读存储器（SPD-EEPROM）中，然后在上电期间复制到AMB上的修复地址缓冲区。

公开(公告)号：US20090137070A1

公开(公告)日：2009-05-28

申请号：US11944551

申请日：2007-11-23

申请人： Ramon S. Co ,  Mike Chen ,  David Sun

发明人： Ramon S. Co ,  Mike Chen ,  David Sun

IPC分类号： H01L21/66

CPC分类号： G11C29/886 ,  G11C5/04 ,  G11C29/06 ,  G11C29/44 ,  G11C29/56 ,  G11C29/56016 ,  G11C29/88 ,  H01L22/20 ,  H01L2924/0002 ,  H01L2924/014 ,  H01L2924/00

摘要： A manufacturing method makes memory modules from partially-good DRAM chips soldered to its substrate. The partially-good DRAM chips have a number of defective memory cells that is below a test threshold, such as 10%. Packaged DRAM chips are optionally pre-screened and considered to pass when the number of defects found is less than the test threshold. A defect table is created during testing and written to a serial-presence-detect electrically-erasable read-only memory (SPD-EEPROM) on the memory module. The memory module is finally tested on a target-system tester that reads the defect table during booting, and redirects memory access to defective memory locations identified by the defect table. The memory modules may be burned in or tested at various temperatures and voltages to increase reliability.

摘要翻译： 制造方法使得部分良好的DRAM芯片的存储器模块焊接到其衬底。 部分良好的DRAM芯片具有低于测试阈值的多个缺陷存储器单元，例如10％。 当发现的缺陷数量小于测试阈值时，封装的DRAM芯片可以预先筛选并被认为是通过的。 在测试期间创建缺陷表，并将其写入存储器模块上的串行存在检测电可擦除只读存储器（SPD-EEPROM）。 内存模块最终在目标系统测试器上进行测试，该测试仪在引导期间读取缺陷表，并将存储器访问重定向到由缺陷表识别的缺陷存储器位置。 存储器模块可以在各种温度和电压下燃烧或测试以增加可靠性。

公开(公告)号：US20090073788A1

公开(公告)日：2009-03-19

申请号：US12275957

申请日：2008-11-21

申请人： Ramon S. Co ,  David Sun

发明人： Ramon S. Co ,  David Sun

IPC分类号： G11C29/00 ,  G11C8/00

CPC分类号： G11C5/04 ,  G11C29/808 ,  G11C29/88

摘要： A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module. The AMB fully buffers memory requests that are sent as serial packets over southbound lanes from a host. Memory-access addresses are extracted from the serial packets by the AMB. The repair controller compares the memory-access addresses to repair addresses and diverts access from defective memory chips to a spare memory for the repair addresses. The repair addresses can be located during testing of the memory module and programmed into a repair address buffer on the AMB. The repair addresses could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to the repair address buffer on the AMB during power-up.

摘要翻译： 修复全缓冲存储器模块可以具有存在诸如单位错误等缺陷的存储器芯片。 修复控制器被添加到内存模块的高级内存缓冲区（AMB）中。 AMB完全缓冲从主机通过南行车道作为串行数据包发送的内存请求。 AMB从串行数据包中提取存储器访问地址。 修复控制器将存储器访问地址与修复地址进行比较，并将从缺陷存储器芯片的访问转移到用于修复地址的备用存储器。 修复地址可以在测试存储器模块期间定位并编程到AMB上的修复地址缓冲区中。 修复地址可以首先编程到存储器模块上的串行存在检测电可擦除可编程只读存储器（SPD-EEPROM）中，然后在上电期间复制到AMB上的修复地址缓冲区。

公开(公告)号：US07478290B2

公开(公告)日：2009-01-13

申请号：US11309296

申请日：2006-07-24

申请人： Ramon S. Co ,  Tat Leung Lai ,  David Sun

发明人： Ramon S. Co ,  Tat Leung Lai ,  David Sun

IPC分类号： G11C29/00

CPC分类号： G11C29/56 ,  G11C29/56016 ,  G11C2029/5602

摘要： Memory chips are tested by insertion into a chip test socket on a test adapter board that is mounted to the reverse or solder-side of a personal computer motherboard. A memory module socket is removed from the motherboard, and adapter pins are inserted into holes for the removed memory module socket, but from the reverse (solder) side of the motherboard. The adapter pins connect to the test adapter board either directly, through a connector plug, or through an intervening adapter board. The test adapter board has soldered onto it additional memory chips and buffer chips on a memory module, such as an Advanced Memory Buffer (AMB) for a fully-buffered memory module. The built-in-self-test (BIST) feature of the AMB may be used to test the memory chip under test in the chip test socket, or the processor on the motherboard may write and read the memory chip.

摘要翻译： 通过插入到安装在个人计算机主板的反面或焊接侧的测试适配器板上的芯片测试插座来测试存储芯片。 内存模块插座从主板上拆下，并将适配器插头插入拆卸的内存模块插槽的孔中，但插入主板背面（焊料）侧。 适配器引脚直接连接到测试适配器板，通过连接器插头或插入适配器板。 测试适配器板已经在内存模块上焊接了额外的存储器芯片和缓冲芯片，例如用于全缓冲存储器模块的高级存储器缓冲器（AMB）。 AMB的内置自检（BIST）功能可用于测试芯片测试插座中的待测内存芯片，或者主板上的处理器可能会写入和读取内存芯片。

公开(公告)号：US07473568B2

公开(公告)日：2009-01-06

申请号：US11308869

申请日：2006-05-17

申请人： Ramon S. Co ,  David Sun

发明人： Ramon S. Co ,  David Sun

IPC分类号： H01L21/66

CPC分类号： G01R31/3016 ,  G01R31/318513 ,  G11C5/04 ,  G11C11/401 ,  G11C29/06 ,  G11C29/56 ,  G11C29/56016 ,  G11C2029/0405 ,  G11C2029/5602

摘要： Reliable memory modules are assembled from partially-tested memory chips that are neither individually burned-in nor fully tested. Instead, individual memory chips are partially tested to screen out gross failures and then assembled into memory modules that are inserted into memory-module burn-in boards and placed into a burn-in oven. The memory modules are stressed during burn-in by high temperatures and applied voltages. After burn-in, the memory modules are removed from the memory-module burn-in boards and extensively tested. Functional tests include many test patterns to test all memory locations in the partially-tested memory chips on the memory modules. Tests are performed at corner conditions such as high temperature and voltage. Infant mortality and single-bit faults are detected by the functional tests after module burn-in. The number of insertions into burn-in boards is reduced by the number of memory chips per module minus one, so handling and test costs are reduced.

摘要翻译： 可靠的内存模块由部分测试的内存芯片进行组装，这些内存芯片既不单独烧录也不完全测试。 相反，单独的内存芯片被部分测试以筛选出总体故障，然后组装到插入存储模块老化板并放入老化炉中的存储器模块中。 存储器模块在高温和施加电压老化期间受到应力。 老化之后，将内存模块从内存模块老化板中取出并经过广泛测试。 功能测试包括许多测试模式，用于测试内存模块部分测试的内存芯片中的所有内存位置。 在诸如高温和高压的拐角条件下进行试验。 模块烧录后的功能测试检测到婴儿死亡率和单位故障。 插入老化板的数量减少了每个模块的存储器芯片数减去1个，因此降低了处理和测试成本。

公开(公告)号：US07379361B2

公开(公告)日：2008-05-27

申请号：US11309297

申请日：2006-07-24

申请人： Ramon S. Co ,  David Sun

发明人： Ramon S. Co ,  David Sun

IPC分类号： G11C29/00

CPC分类号： G11C5/04 ,  G11C29/808 ,  G11C29/88

摘要： A repairing fully-buffered memory module can have memory chips with some defects such as single-bit errors. A repair controller is added to the Advanced Memory Buffer (AMB) on the memory module. The AMB fully buffers memory requests that are sent as serial packets over southbound lanes from a host. Memory-access addresses are extracted from the serial packets by the AMB. The repair controller compares the memory-access addresses to repair addresses and diverts access from defective memory chips to a spare memory for the repair addresses. The repair addresses can be located during testing of the memory module and programmed into a repair address buffer on the AMB. The repair addresses could be first programmed into a serial-presence-detect electrically-erasable programmable read-only memory (SPD-EEPROM) on the memory module, and then copied to the repair address buffer on the AMB during power-up.

摘要翻译： 修复全缓冲存储器模块可以具有存在诸如单位错误等缺陷的存储器芯片。 修复控制器被添加到内存模块的高级内存缓冲区（AMB）中。 AMB完全缓冲从主机通过南行车道作为串行数据包发送的内存请求。 AMB从串行数据包中提取存储器访问地址。 修复控制器将存储器访问地址与修复地址进行比较，并将从缺陷存储器芯片的访问转移到用于修复地址的备用存储器。 修复地址可以在测试存储器模块期间定位并编程到AMB上的修复地址缓冲区。 修复地址可以首先编程到存储器模块上的串行存在检测电可擦除可编程只读存储器（SPD-EEPROM）中，然后在上电期间复制到AMB上的修复地址缓冲区。

公开(公告)号：US07277337B1

公开(公告)日：2007-10-02

申请号：US11309782

申请日：2006-09-25

申请人： Ramon S. Co ,  Mike Chen ,  David Sun

发明人： Ramon S. Co ,  Mike Chen ,  David Sun

IPC分类号： G11C29/00

CPC分类号： G11C29/883 ,  G11C5/04 ,  G11C29/88 ,  G11C2029/4402

摘要： A downgraded memory module has downgraded DRAM chips soldered to its substrate. The downgraded DRAM chips have a defective memory cell in a logical quadrant of the memory. A physical MSB is a row address present on a non-downgraded DRAM of size S but not used on a downgraded DRAM size S/2. The physical MSB and a second address pin are non-multiplexed address pins that do not carry column addresses. The physical MSB and the second address pin logically divided the DRAM into quadrants. Two good quadrants without defects are selected, and jumpers on the memory module drive the physical MSB and the second address pin with signals that select only these two quadrants and disable access to quadrants containing defects. DRAM chips can be marked or sorted into bins for combinations of good quadrants. Downgraded memory modules have all DRAM chips from the same bin that share jumper settings.

摘要翻译： 降级的存储器模块将DRAM芯片降级到其基板。 降级的DRAM芯片在存储器的逻辑象限中具有有缺陷的存储单元。 物理MSB是存在于尺寸为S的未降级DRAM上但不降级DRAM大小S / 2的行地址。 物理MSB和第二个地址引脚是不带有列地址的非多路复用地址引脚。 物理MSB和第二个地址引脚将DRAM逻辑划分为象限。 选择没有缺陷的两个良好象限，并且存储器模块上的跳线使用仅选择这两个象限的信号驱动物理MSB和第二个地址引脚，并禁止访问包含缺陷的象限。 可以将DRAM芯片标记或分类到用于良好象限组合的箱中。 降级的内存模块具有来自共享跳线设置的同一个bin的所有DRAM芯片。

公开(公告)号：US07272774B2

公开(公告)日：2007-09-18

申请号：US10709156

申请日：2004-04-16

申请人： Ramon S. Co ,  Tat Leung Lai ,  David Sun

发明人： Ramon S. Co ,  Tat Leung Lai ,  David Sun

IPC分类号： G11C29/00 ,  G06F11/00

CPC分类号： G11C29/24 ,  G06F11/2215 ,  G11C5/04 ,  G11C2029/5602

摘要： Memory modules with an extra dynamic-random-access memory (DRAM) chip for storing error-correction code (ECC) are tested on a personal computer (PC) motherboard tester using a cross-over extender card inserted into a memory module socket on the motherboard. ECC code generated on the motherboard is normally stored in the extra ECC DRAM chip, preventing test patterns such as checkerboards and walking-ones to be written directly to the ECC DRAM chip. During testing, the cross-over extender card routes signals from the motherboard for one of the data DRAM chips to the ECC DRAM chip, while the ECC code is routed to one of the data DRAM chips. The checkerboard or other test pattern is thus written and read from the ECC DRAM chip that normally stores the ECC code. The cross-over extender card can be hardwired, or can have a switch to allow normal operation or testing of the ECC DRAM chip.

摘要翻译： 具有用于存储纠错码（ECC）的额外动态随机存取存储器（DRAM）芯片的存储器模块在个人计算机（PC）主板测试器上使用插入到内存模块插槽中的跨越延长卡进行测试 母板。 在主板上产生的ECC代码通常存储在额外的ECC DRAM芯片中，防止诸如棋盘和步行的测试图案直接写入ECC DRAM芯片。 在测试期间，交叉扩展卡将来自主板的信号从数据DRAM芯片中的一个传送到ECC DRAM芯片，而ECC代码被路由到数据DRAM芯片之一。 因此，棋盘或其他测试图案由通常存储ECC代码的ECC DRAM芯片写入和读出。 交叉扩展卡可以是硬连线的，或者可以有开关来允许ECC DRAM芯片的正常操作或测试。

公开(公告)号：US06824410B1

公开(公告)日：2004-11-30

申请号：US10709154

申请日：2004-04-16

申请人： Ramon S. Co ,  Tat Leung Lai ,  David Sun

发明人： Ramon S. Co ,  Tat Leung Lai ,  David Sun

IPC分类号： H01R1362

CPC分类号： H01R12/88 ,  H01R2201/20

摘要： A test socket for testing memory modules requires little or no insertion force. A base holds a funnel-shaped guide that guides the edge of the memory module into a desired position. Two housing halves are connected to the base by one or more hinges. The housing halves pivot around the hinges to open and close the test socket. Linkages, springs, or solenoids move the housing halves. Metal contact pads on flexible membranes are attached to each housing half and clamp onto contact pads on an inserted memory module when the housing halves are closed. Scooped vise clamps can be used to pinch together the ends of the housing halves to close the test socket. More test sockets can be fitted into a smaller pitch using the scooped vise clamps since the solenoids are along the longer axis of the test socket.

摘要翻译： 用于测试内存模块的测试插座很少或没有插入力。 基座保持将存储器模块的边缘引导到期望位置的漏斗形引导件。 两个壳体半部通过一个或多个铰链连接到基座。 外壳半部围绕铰链枢转以打开和关闭测试插座。 连杆，弹簧或螺线管移动外壳半部。 柔性膜上的金属接触垫连接到每个壳体半部，并且当外壳半部封闭时，夹紧在插入的存储器模块上的接触垫上。 捣实的虎钳夹具可用于将外壳半部的端部夹在一起以关闭测试插座。 由于螺线管沿着测试插座的较长的轴线，所以使用舀起的虎钳夹具可以将更多的测试插座安装到更小的间距中。