公开(公告)号：US20060017109A1

公开(公告)日：2006-01-26

申请号：US11201373

申请日：2005-08-10

Applicant: Randy Yach ,  Greg Dix

Inventor： Randy Yach ,  Greg Dix

IPC: H01L23/62

CPC classification number: H01L27/0259

Abstract: A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the input and/or output circuits. The ESD-protection structure is able to absorb high current from these ESD events without snapback that would compromise operation of the higher voltage inputs and/or outputs of the integrated circuit. The ESD-protection structure will conduct when an ESD event occurs at a voltage above a controlled breakdown voltage of an electronic device, e.g., diode, in the ESD protection structure. Conduction of current from an ESD event having a voltage above the electronic device controlled breakdown voltage may be through another electronic device, e.g., transistor, having high current conduction capabilities, in the ESD-protection structure that may be controlled (triggered) by the device (e.g., diode) determining the controlled breakdown voltage (at which the ESD voltage is clamped to a desired value). The high voltage ESD-protection structure may be located substantially under the bond pad and may also include a low capacitance forward diode structure between the bond pad and the ESD clamp circuit.

Abstract translation: 高压ESD保护结构用于通过在可能导致破坏性击穿的电压下进行受控击穿电压来保护连接到集成电路接合焊盘的输入或输出的精细晶体管电路免受破坏性高电压ESD事件的影响 的输入和/或输出电路。 ESD保护结构能够吸收来自这些ESD事件的高电流，而不会产生危及集成电路的较高电压输入和/或输出的操作的快速恢复。 当ESD事件发生在高于ESD保护结构中电子器件（例如二极管）的受控击穿电压的电压时，ESD保护结构将导通。 来自具有高于电子器件受控击穿电压的电压的ESD事件的电流的导通可以通过可由该器件控制（触发）的ESD保护结构中的另一电子器件，例如具有高电流传导能力的晶体管 （例如，二极管）确定受控击穿电压（ESD电压被钳位到期望值）。 高压ESD保护结构可以基本上位于接合焊盘下方，并且还可以包括在接合焊盘和ESD钳位电路之间的低电容正向二极管结构。

公开(公告)号：US20050212052A1

公开(公告)日：2005-09-29

申请号：US10809659

申请日：2004-03-25

Applicant: Randy Yach ,  Greg Dix

Inventor： Randy Yach ,  Greg Dix

IPC: H01L23/62 ,  H01L27/02

CPC classification number: H01L27/0259

Abstract: A high voltage ESD-protection structure is used to protect delicate transistor circuits connected to an input or output of an integrated circuit bond pad from destructive high voltage ESD events by conducting at a controlled breakdown voltage that is less than a voltage that may cause destructive breakdown of the input and/or output circuits. The ESD-protection structure is able to absorb high current from these ESD events without snapback that would compromise operation of the higher voltage inputs and/or outputs of the integrated circuit. The ESD-protection structure will conduct when an ESD event occurs at a voltage above a controlled breakdown voltage of an electronic device, e.g., diode, in the ESD protection structure. Conduction of current from an ESD event having a voltage above the electronic device controlled breakdown voltage may be through another electronic device, e.g., transistor, having high current conduction capabilities, in the ESD-protection structure that may be controlled (triggered) by the device (e.g., diode) determining the controlled breakdown voltage (at which the ESD voltage is clamped to a desired value). The high voltage ESD-protection structure may be located substantially under the bond pad and may also include a low capacitance forward diode structure between the bond pad and the ESD clamp circuit.

Abstract translation: 高压ESD保护结构用于通过在可能导致破坏性击穿的电压下进行受控击穿电压来保护连接到集成电路接合焊盘的输入或输出的精细晶体管电路免受破坏性高电压ESD事件的影响 的输入和/或输出电路。 ESD保护结构能够吸收来自这些ESD事件的高电流，而不会产生危及集成电路的较高电压输入和/或输出的操作的快速恢复。 当ESD事件发生在高于ESD保护结构中电子器件（例如二极管）的受控击穿电压的电压时，ESD保护结构将导通。 来自具有高于电子器件受控击穿电压的电压的ESD事件的电流的导通可以通过可由该器件控制（触发）的ESD保护结构中的另一电子器件，例如具有高电流传导能力的晶体管 （例如，二极管）确定受控击穿电压（ESD电压被钳位到期望值）。 高压ESD保护结构可以基本上位于接合焊盘下方，并且还可以包括在接合焊盘和ESD钳位电路之间的低电容正向二极管结构。

公开(公告)号：US08427075B2

公开(公告)日：2013-04-23

申请号：US12622745

申请日：2009-11-20

Applicant: Ward R. Brown ,  Randy Yach

Inventor： Ward R. Brown ,  Randy Yach

IPC: H05B37/02

CPC classification number: H05B33/0806 ,  H05B33/0815

Abstract: A constant current output sink or source eliminates a current limiting series resistor for a light emitting diode (LED) and maintains a constant light intensity from the LED for all operating and manufacturing variables of a digital device since the current through the LED is maintained at a constant value. The constant current output sink or source may be programmable for selection of a constant current value from a plurality of constant current values available.

Abstract translation: 恒定电流输出接收器或源极消除了用于发光二极管（LED）的限流串联电阻器，并且为了数字器件的所有操作和制造变量而保持来自LED的恒定的光强度，因为通过LED的电流维持在 恒定值。 恒流输出接收器或源可以是可编程的，用于从可用的多个恒定电流值中选择恒定电流值。

公开(公告)号：US07876540B2

公开(公告)日：2011-01-25

申请号：US12174802

申请日：2008-07-17

Applicant: Philippe Deval ,  Patrick Besseux ,  Randy Yach

Inventor： Philippe Deval ,  Patrick Besseux ,  Randy Yach

IPC: H02H9/00

CPC classification number: H01L27/0266 ,  H02H9/046

Abstract: Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capacitive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.

公开(公告)号：US20070140008A1

公开(公告)日：2007-06-21

申请号：US11314504

申请日：2005-12-21

Applicant: Jeffrey Shields ,  Kent Hewitt ,  Donald Gerber ,  Randy Yach

Inventor： Jeffrey Shields ,  Kent Hewitt ,  Donald Gerber ,  Randy Yach

IPC: G11C16/04 ,  G11C11/34

CPC classification number: H01L27/115 ,  G11C16/0425 ,  H01L27/11521 ,  H01L27/11524

Abstract: An array of N-channel memory cells may be separated into independently programmable memory segments by creating multiple, electrically isolated P-wells upon which the memory segments are fabricated. The multiple, electrically isolated P-wells may be created, for example, by p-n junction isolation or dielectric isolation.

Abstract translation: N沟道存储器单元的阵列可以通过在其上制造存储器段的多个电隔离的P阱分离成独立可编程的存储器段。 多个电隔离的P阱可以例如通过p-n结隔离或电介质隔离来产生。

公开(公告)号：US20070007597A1

公开(公告)日：2007-01-11

申请号：US11215775

申请日：2005-08-30

Applicant: Randy Yach ,  Philippe Deval

Inventor： Randy Yach ,  Philippe Deval

IPC: H01L23/62

CPC classification number: H01L27/0266

Abstract: An electrostatic discharge (ESD) structure having increased voltage withstand at an output terminal of an integrated circuit device has a thin gate oxide layer metal oxide semiconductor (MOS) device coupled in series with a thicker gate oxide layer MOS device. The thin gate oxide layer MOS device may be controlled by a low voltage control circuit of the integrated circuit. The thicker gate oxide layer MOS device may be coupled to an output of the integrated circuit device or a bipolar transistor may be coupled between the output of the integrated circuit device and the thicker gate oxide layer MOS device. The thin gate oxide layer and thicker gate oxide layer MOS devices may be coupled in series.

Abstract translation: 在集成电路器件的输出端具有增加的耐压的静电放电（ESD）结构具有与较厚栅极氧化物层MOS器件串联耦合的薄栅极氧化物层金属氧化物半导体（MOS）器件。 薄栅氧化层MOS器件可以由集成电路的低压控制电路来控制。 较厚的栅极氧化物层MOS器件可以耦合到集成电路器件的输出，或者双极晶体管可以耦合在集成电路器件的输出和较厚栅极氧化物层MOS器件之间。 薄栅极氧化物层和较厚栅极氧化物层MOS器件可以串联耦合。

公开(公告)号：US20140134574A1

公开(公告)日：2014-05-15

申请号：US14160840

申请日：2014-01-22

Applicant: Randy Yach

Inventor： Randy Yach ,  Paul Katz

IPC: F41G3/26

CPC classification number: F41G3/2655 ,  F41A33/02 ,  F41J5/00

Abstract: Laser target practice using an ultra-violet light emitting laser that is pulsed on when a weapon trigger is pulled. The UV laser light pulse illuminates a spot on a target having a coating of phosphorescent material on a face thereof. The phosphorescent material within the illuminated spot glows for a certain time thereby visually indicating a location of the spot on the target. The UV laser light pulse may also illuminate a spot on a target having a photochromic paint coatings on a face thereof. The photochromic paint coatings within the illuminated spot changes color thereby indicating a location of the spot on the target.

Abstract translation: 使用在武器扳机被拉动时脉冲的紫外光发射激光的激光瞄准练习。 紫外激光脉冲在其表面上照射具有磷光材料涂层的靶上的斑点。 照明光斑内的磷光材料发光一定时间，从而可视地显示光斑在靶上的位置。 UV激光脉冲也可以照射其表面上具有光致变色涂料的靶上的斑点。 照明区域内的光致变色涂料涂层改变颜色，从而指示目标点上的位置。

公开(公告)号：US07885047B2

公开(公告)日：2011-02-08

申请号：US12174903

申请日：2008-07-17

Applicant: Philippe Deval ,  Patrick Besseux ,  Randy Yach

Inventor： Philippe Deval ,  Patrick Besseux ,  Randy Yach

IPC: H02H9/00

CPC classification number: H01L27/0266 ,  H02H9/046

Abstract: Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capacitive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.

Abstract translation: 器件接口的自适应静电放电（ESD）保护在处理或安装到系统或从系统中移除时具有非常好的ESD鲁棒性。 并且当其在系统中可操作时，具有对DPI，电磁干扰（EMI）等的强大的抗扰性。 在外部连接上没有（或低电平）DPI时，ESD保护金属氧化物半导体（MOS）器件的漏极和栅极之间存在显着的电容耦合，以增强ESD保护和较低的反冲电压。 。 因此当在外部连接上检测到显着的DPI / EMI信号时，MOS ESD保护器件的漏极和栅极之间的电容耦合被断开，旁路或衰减，从而增强了器件的DPI / EMI抗扰度。

公开(公告)号：US20090128970A1

公开(公告)日：2009-05-21

申请号：US12174903

申请日：2008-07-17

Applicant: Philippe Deval ,  Patrick Besseux ,  Randy Yach

Inventor： Philippe Deval ,  Patrick Besseux ,  Randy Yach

IPC: H02H9/00

CPC classification number: H01L27/0266 ,  H02H9/046

Abstract: Adaptive electrostatic discharge (ESD) protection of a device interface has very good ESD robustness when it is handled or when installed into or removed from a system. And has robust immunity to DPI, electromagnetic interference (EMI) and the like, when it is operational in a system. There is a significant capacitive coupling between the drain and gate of a ESD protection metal oxide semiconductor (MOS) device to enhance ESD protection and lower snap back voltage thereof whenever there is no (or a low level) DPI on the external connection to be protected. Whereupon when a significant DPI/EMI signal is detected on the external connection, the capa citive coupling between the drain and gate of the MOS ESD protection device is disconnected, bypassed or attenuated so that DPI/EMI immunity of the device is enhanced.

公开(公告)号：US20070094454A1

公开(公告)日：2007-04-26

申请号：US11254373

申请日：2005-10-20

Applicant: Steven Brundula ,  Randy Yach ,  Sam Alexander ,  Mike Pyska ,  Douglas Chaffee

Inventor： Steven Brundula ,  Randy Yach ,  Sam Alexander ,  Mike Pyska ,  Douglas Chaffee

IPC: G06F13/00

CPC classification number: G06F12/06 ,  G06F12/0638 ,  Y02D10/13

Abstract: An integrated circuit digital processor is coupled to either a main program memory or a secondary program memory, wherein the secondary program memory may be low power, high reliability, non-volatile and/or fast memory that may store a limited number of critical program instructions and data for execution by the digital processor. A program memory switch may couple the digital processor to either the main program memory or the secondary program memory. This is particularly advantageous in that the secondary program memory may have attributes not economically feasible with the main program memory. A program memory controller may handle the selection of which of these memories that the digital processor is using to obtain its program instructions, and necessary control signals for switching and operation thereof.

Abstract translation: 集成电路数字处理器耦合到主程序存储器或辅助程序存储器，其中次要程序存储器可以是可以存储有限数量的关键程序指令的低功率，高可靠性，非易失性和/或快速存储器 以及由数字处理器执行的数据。 程序存储器开关可以将数字处理器耦合到主程序存储器或辅助程序存储器。 这是特别有利的，因为次程序存储器可能具有在主程序存储器中经济可行的属性。 程序存储器控制器可以处理数字处理器正在使用的这些存储器中的哪一个的选择以获得其程序指令，以及用于其切换和操作的必要控制信号。