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公开(公告)号：US09628021B2
公开(公告)日：2017-04-18
申请号：US15043950
申请日：2016-02-15
Applicant: Renesas Electronics Corporation
Inventor： Osamu Ozawa , Masashi Horiguchi , Yuichi Okuda , Akihito Anzai
CPC classification number: H03B5/32 , H02H7/20 , H03B5/364 , H03B2200/0088 , H03B2202/03 , H03B2202/082 , H03B2202/084 , H05K1/181 , H05K2201/10075
Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.
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公开(公告)号：US20160164461A1
公开(公告)日：2016-06-09
申请号：US15043950
申请日：2016-02-15
Applicant: Renesas Electronics Corporation
Inventor： Osamu Ozawa , Masashi Horiguchi , Yuichi Okuda , Akihito Anzai
CPC classification number: H03B5/32 , H02H7/20 , H03B5/364 , H03B2200/0088 , H03B2202/03 , H03B2202/082 , H03B2202/084 , H05K1/181 , H05K2201/10075
Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.
Abstract translation: 用于振荡输入信号的布线图案和用于振荡输出信号的布线图案设置在印刷电路板上，并且用于接地电源电压的布线图案布置在它们之间的区域中。 在用于振荡输入信号的布线图案和振荡输出信号的布线图案之间连接石英晶体单元，并且将其作为负载电容器的电容器的一端连接到地电源电压的布线图案。 此外，为了包围这些布线图案，布置有用于VSS的布线图案，并且除此之外，还布置有用于VSS的布线图案。 通过这种方式，可以实现XIN节点和XOUT节点之间的寄生电容的减小，这些节点等的噪声容限的改善。
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公开(公告)号：US09300248B2
公开(公告)日：2016-03-29
申请号：US14263030
申请日：2014-04-28
Applicant: Renesas Electronics Corporation
Inventor： Osamu Ozawa , Masashi Horiguchi , Yuichi Okuda , Akihito Anzai
CPC classification number: H03B5/32 , H02H7/20 , H03B5/364 , H03B2200/0088 , H03B2202/03 , H03B2202/082 , H03B2202/084 , H05K1/181 , H05K2201/10075
Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.
Abstract translation: 用于振荡输入信号的布线图案和用于振荡输出信号的布线图案设置在印刷电路板上，并且用于接地电源电压的布线图案布置在它们之间的区域中。 在用于振荡输入信号的布线图案和振荡输出信号的布线图案之间连接石英晶体单元，并且将其作为负载电容器的电容器的一端连接到地电源电压的布线图案。 此外，为了包围这些布线图案，布置有用于VSS的布线图案，并且除此之外，还布置有用于VSS的布线图案。 通过这种方式，可以实现XIN节点和XOUT节点之间的寄生电容的减小，这些节点等的噪声容限的改善。
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公开(公告)号：US20140232476A1
公开(公告)日：2014-08-21
申请号：US14263030
申请日：2014-04-28
Applicant: Renesas Electronics Corporation
Inventor： Osamu Ozawa , Masashi Horiguchi , Yuichi Okuda , Akihito Anzai
CPC classification number: H03B5/32 , H02H7/20 , H03B5/364 , H03B2200/0088 , H03B2202/03 , H03B2202/082 , H03B2202/084 , H05K1/181 , H05K2201/10075
Abstract: A wiring pattern for oscillation input signal and a wiring pattern for oscillation output signal are provided on a printed circuit board, and a wiring pattern for ground power source voltage is arranged in a region therebetween. A quartz crystal unit is connected between the wiring pattern for oscillation input signal and the wiring pattern for oscillation output signal and one ends of capacitors serving as load capacitors thereof are connected to the wiring pattern for ground power source voltage. Further, a wiring pattern for VSS is arranged so as to enclose these wiring patterns, and a wiring pattern for VSS is arranged also in a lower layer in addition thereto. By this means, reduction of a parasitic capacitance between an XIN node and an XOUT node, improvement in noise tolerance of these nodes and others can be achieved.
Abstract translation: 用于振荡输入信号的布线图案和用于振荡输出信号的布线图案设置在印刷电路板上，并且用于接地电源电压的布线图案布置在它们之间的区域中。 在用于振荡输入信号的布线图案和振荡输出信号的布线图案之间连接石英晶体单元，并且其作为负载电容器的电容器的一端连接到地电源电压的布线图案。 此外，为了包围这些布线图案，布置有用于VSS的布线图案，并且除此之外，还布置有用于VSS的布线图案。 通过这种方式，可以实现XIN节点和XOUT节点之间的寄生电容的减小，这些节点等的噪声容限的改善。
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