公开(公告)号：US20150220095A1

公开(公告)日：2015-08-06

申请号：US14684889

申请日：2015-04-13

Applicant: Renesas Electronics Corporation

Inventor： Masafumi ONOUCHI ,  Kazuo OTSUGA ,  Yasuto IGARASHI ,  Sadayuki MORITA ,  Koichiro ISHIBASHI ,  Kazumasa YANAGISAWA

IPC: G05F1/59

CPC classification number: G05F1/59 ,  G06F1/26 ,  H01L23/5286 ,  H01L2924/0002 ,  H02M2001/0045 ,  H03K17/102 ,  H01L2924/00

Abstract: A semiconductor integrated circuit includes a plurality of output transistors each controlling the magnitude of an output voltage relative to the magnitude of a load current according to a control value indicated by an impedance control signal applied to a control terminal, a voltage monitor circuit outputting an output voltage monitor value indicating a voltage value of the output voltage, and a control circuit controlling the magnitude of the control value according to the magnitude of an error value between a reference voltage indicating a target value of the output voltage and the output voltage monitor value, and controls based on the control value whether any of such transistors be brought to a conducting state. The control circuit increases a change step of the control value relative to the error value during a predetermined period according to prenotification signals for notifying a change of the load current in advance.

Abstract translation: 半导体集成电路包括多个输出晶体管，每个输出晶体管根据施加到控制端子的阻抗控制信号所指示的控制值来控制输出电压的大小相对于负载电流的大小，输出输出的电压监视电路 表示输出电压的电压值的电压监视值，以及根据表示输出电压的目标值的基准电压与输出电压监视值之间的误差值的大小来控制控制值的大小的控制电路， 并且基于控制值来控制是否任何这种晶体管进入导通状态。 控制电路根据预先通知负载电流变化的预通知信号，在预定期间内增加控制值相对于误差值的变化步长。

公开(公告)号：US20130214339A1

公开(公告)日：2013-08-22

申请号：US13750928

申请日：2013-01-25

Applicant: Renesas Electronics Corporation

Inventor： Yoshinori Tanaka ,  Masahiro Shimizu ,  Hideaki Arima ,  Sadayuki MORITA

IPC: H01L27/06

CPC classification number: H01L27/0629 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10844 ,  H01L27/10852 ,  H01L27/10894 ,  H01L28/91

Abstract: A semiconductor device, including a memory cell region and a peripheral circuit region, comprises an insulating film, having an upper surface formed on a major surface of a semiconductor substrate to extend from a memory cell region to a peripheral circuit region thereof. A capacitor lower electrode is formed in the memory cell region to upwardly extend beyond the upper surface of the insulating film on the major surface of the semiconductor substrate. A capacitor upper electrode is formed on the capacitor lower electrode through a dielectric film, to extend onto the upper surface of the insulating film. The capacitor lower electrode includes a capacitor lower electrode part having a top surface and a bottom surface. The upper surface of the insulating film is located between the top and bottom surfaces of the capacitor lower electrode part.

Abstract translation: 包括存储单元区域和外围电路区域的半导体器件包括绝缘膜，其具有形成在半导体衬底的主表面上的上表面，以从存储单元区域延伸到其外围电路区域。 在存储单元区域中形成电容器下电极，以向上延伸超过半导体衬底的主表面上的绝缘膜的上表面。 电容器上电极通过电介质膜形成在电容器下电极上，延伸到绝缘膜的上表面。 电容器下电极包括具有顶表面和底表面的电容器下电极部分。 绝缘膜的上表面位于电容器下电极部的顶表面和底表面之间。