公开(公告)号：US20240421166A1

公开(公告)日：2024-12-19

申请号：US18641596

申请日：2024-04-22

Applicant: Renesas Electronics Corporation

Inventor： Makoto KOSHIMIZU ,  Shigeki TSUBAKI

IPC: H01L27/144 ,  H01L21/762 ,  H01L23/528 ,  H01L29/66 ,  H01L29/78 ,  H01L31/02

Abstract: An anode region and a cathode region of a photodiode are formed in a semiconductor substrate. At a main surface of the semiconductor substrate, a plurality of first STI regions are formed on the cathode region, and an oxide film is formed between the plurality of first STI regions. A shield electrode is formed on the plurality of first STI regions and the oxide film. A thickness of each of the plurality of first STI regions is smaller than a thickness of second STI region.

公开(公告)号：US20150303182A1

公开(公告)日：2015-10-22

申请号：US14686843

申请日：2015-04-15

Applicant: Renesas Electronics Corporation

Inventor： Shigeki TSUBAKI

IPC: H01L27/02 ,  H01L29/06 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12 ,  H01L27/06 ,  H01L29/861

CPC classification number: H01L27/0255 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/6609 ,  H01L29/861

Abstract: The semiconductor device of the present invention includes: a MOSFET having a gate electrode formed via a gate insulating film over a semiconductor layer and source and drain regions formed in the semiconductor layer on both sides of the gate electrode; and a diode. The diode has an n+-type semiconductor region, a p-type semiconductor region and a p+-type semiconductor region. Then, the gate electrode is connected to the n+-type semiconductor region via an n-type semiconductor region formed so as to be connected to the n+-type semiconductor region. Also, the p+-type semiconductor region is connected to a semiconductor layer below the gate electrode. In this way, by providing the diode between the back gate and gate electrode of the MOSFET, breakage of the gate insulating film can be prevented.

Abstract translation: 本发明的半导体器件包括：MOSFET，其具有通过半导体层上的栅极绝缘膜形成的栅电极和形成在栅电极两侧的半导体层中的源极和漏极区域; 和二极管。 二极管具有n +型半导体区域，p型半导体区域和p +型半导体区域。 然后，栅电极经由形成为与n +型半导体区域连接的n型半导体区域连接到n +型半导体区域。 此外，p +型半导体区域连接到栅电极下方的半导体层。 以这种方式，通过在MOSFET的背栅极和栅电极之间设置二极管，可以防止栅极绝缘膜的破损。