公开(公告)号：US20040147137A1

公开(公告)日：2004-07-29

申请号：US10695798

申请日：2003-10-30

Applicant: Renesas Technology Corp.

Inventor： Atsushi Hiraiwa ,  Satoshi Sakai ,  Dai Ishikawa ,  Yoshihiro Ikeda

IPC: H01L021/31

CPC classification number: H01L21/28185 ,  H01L21/28194 ,  H01L21/28273 ,  H01L21/3105 ,  H01L21/823857 ,  H01L27/105 ,  H01L27/11521 ,  H01L27/11526 ,  H01L29/513 ,  H01L29/518 ,  H01L2924/0002 ,  H01L2924/00

Abstract: According to the present invention, an oxide film with the film quality almost equivalent to that of the thermal oxide can be formed by the low-temperature treatment. After removing an insulator on the active region of the substrate which constitutes a semiconductor wafer, an insulator made of, for example, silicon oxide is deposited on the main surface of the semiconductor wafer by the low pressure CVD method. This insulator is a film to form a gate insulator of MISFET in a later step. Subsequently, a plasma treatment is performed in an atmosphere containing oxygen (oxygen plasma treatment) to the insulator in the manner as schematically shown by the arrows. By so doing, the film quality of the insulator formed by the CVD method can be improved to the extent almost equivalent to that of the insulator formed of the thermal oxide.

Abstract translation: 根据本发明，可以通过低温处理形成膜质量几乎等于热氧化物的氧化膜。 在构成半导体晶片的基板的有源区域上去除绝缘体之后，通过低压CVD法在半导体晶片的主表面上沉积由例如氧化硅制成的绝缘体。 该绝缘体是在后续步骤中形成MISFET的栅极绝缘体的膜。 随后，按照箭头示意性地示出的方式，在含有氧的气氛（氧等离子体处理）中对绝缘体进行等离子体处理。 通过这样做，通过CVD方法形成的绝缘体的膜质量可以提高到与由热氧化物形成的绝缘体几乎相同的程度。

公开(公告)号：US20040259306A1

公开(公告)日：2004-12-23

申请号：US10855402

申请日：2004-05-28

Applicant: Renesas Technology Corp.

Inventor： Satoshi Sakai ,  Daichi Matsumoto ,  Katsuyuki Asaka ,  Masatoshi Hasegawa ,  Kazutaka Mori

IPC: H01L021/8242

CPC classification number: H01L27/10894 ,  H01L27/105 ,  H01L27/10814 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1104 ,  H01L27/1116

Abstract: Mutual diffusion of impurities in a gate electrode is suppressed near a boundary between an n-channel type MISFET and a p-channel type MISFET, which adopt a polycide's dual-gate structure. Since a gate electrode of an n-channel type MISFET and a gate electrode of a p-channel type MISFET are of mutually different conductivity types, they are separated to prevent the mutual diffusion of the impurities and are electrically connected to each other via a metallic wiring formed in the following steps. In a step before a gate electrode material is patterned to separate the gate electrodes, the mutual diffusion of the impurities before forming the gate electrodes is prevented by performing no heat treatment at a temperature of 700null C. or higher.

Abstract translation: 在n沟道型MISFET和p型沟道型MISFET之间的边界附近，抑制了栅电极中的杂质的相互扩散，其采用多选择性双栅结构。 由于n沟道型MISFET的栅电极和p沟道型MISFET的栅电极具有相互不同的导电类型，它们被分离以防止杂质的相互扩散，并且通过金属 布线按以下步骤形成。 在将栅电极材料图案化以分离栅电极之前的步骤中，通过在700℃以上的温度下不进行热处理来防止在形成栅电极之前杂质的相互扩散。