公开(公告)号：US07917719B2

公开(公告)日：2011-03-29

申请号：US11566685

申请日：2006-12-04

申请人： Reuven Elhamias ,  David Zehavi ,  Roni Barzilai ,  Vivek Mani ,  Simon Stolero

发明人： Reuven Elhamias ,  David Zehavi ,  Roni Barzilai ,  Vivek Mani ,  Simon Stolero

IPC分类号： G06F12/00

CPC分类号： G06F13/385

摘要： Methods and systems for working around the timeout limitations of physical interface standards for detachable modules. By use of dummy data blocks to keep the bus active, the bus timeout requirements (in either direction) can be spoofed, to thereby permit more complex processing operations to be performed that may exceed the bus timeout of a particular specification. A controller in the memory system deasserts the ready signal and holds the bus connecting the computer system in a “busy” state until the memory system is about to timeout. During a write operation, the controller receives dummy data blocks from the computer system before the write bus timeout period expires, causing the bus timeout period to be reset. During a read operation, the controller sends dummy data blocks to the computer system before the read bus timeout period expires, causing the bus timeout period to be reset.

摘要翻译： 解决可拆卸模块物理接口标准超时限制的方法和系统。 通过使用虚拟数据块来保持总线有效，可以欺骗总线超时要求（在任一方向上），从而允许执行可能超过特定规范的总线超时的更复杂的处理操作。 存储器系统中的控制器取消准备就绪信号并保持连接计算机系统处于“忙”状态的总线，直到存储器系统即将超时。 在写入操作期间，控制器在写入总线超时时间到期之前从计算机系统接收虚拟数据块，导致总线超时周期被复位。 在读操作期间，控制器在读总线超时时间到期之前，向计算机系统发送伪数据块，导致总线超时时间被重置。

公开(公告)号：US20090164681A1

公开(公告)日：2009-06-25

申请号：US11566685

申请日：2006-12-04

申请人： Reuven Elhamias ,  David Zehavi ,  Roni Barzilai ,  Vivek Mani ,  Simon Stolero

发明人： Reuven Elhamias ,  David Zehavi ,  Roni Barzilai ,  Vivek Mani ,  Simon Stolero

IPC分类号： G06F13/372

CPC分类号： G06F13/385

摘要： Methods and systems for working around the timeout limitations of physical interface standards for detachable modules. By use of dummy data blocks to keep the bus active, the bus timeout requirements (in either direction) can be spoofed, to thereby permit more complex processing operations to be performed, which otherwise might not fit reliably within the timeout period. This permits a memory system to execute applications or process data for a time period that may exceed the bus timeout of a particular specification. A controller in the memory system deasserts the ready signal and holds the bus connecting the computer system in a “busy” state until the memory system is about to timeout. During a write operation, the controller receives dummy data blocks from the computer system before the write bus timeout period expires, causing the bus timeout period to be reset. During a read operation, the controller sends dummy data blocks to the computer system before the read bus timeout period expires, causing the bus timeout period to be reset.

摘要翻译： 解决可拆卸模块物理接口标准超时限制的方法和系统。 通过使用虚拟数据块来保持总线有效，可以欺骗总线超时要求（在任一方向上），从而允许执行更复杂的处理操作，否则在超时时间段内可能不可靠。 这允许存储器系统在可能超过特定规范的总线超时的时间段内执行应用或处理数据。 存储器系统中的控制器取消准备就绪信号并保持连接计算机系统处于“忙”状态的总线，直到存储器系统即将超时。 在写入操作期间，控制器在写入总线超时时间到期之前从计算机系统接收虚拟数据块，导致总线超时周期被复位。 在读操作期间，控制器在读总线超时时间到期之前，向计算机系统发送伪数据块，导致总线超时时间被重置。