公开(公告)号：US07987399B2

公开(公告)日：2011-07-26

申请号：US11758708

申请日：2007-06-06

申请人： Richard Dono ,  Roger D. Weekly

发明人： Richard Dono ,  Roger D. Weekly

IPC分类号： G01R31/28

CPC分类号： G01R31/318533

摘要： A test card system for use in product development includes a device under test (DUT). The DUT comprises: a mount plane; a power input port coupled to the mount plane; a JTAG input port coupled to the mount plane; a clock signal distribution network coupled to the JTAG input port; a plurality of latches coupled to the clock signal distribution network and the power input port; and an output port coupled to the plurality of latches. A test card (TC) couples to the DUT, comprising: a JTAG interface coupled to the DUT JTAG input port and configured to provide test data to the DUT; a clock module coupled to the DUT clock signal distribution network and configured to generate a clock signal; and an analysis module coupled to the DUT output port and configured to receive data from the DUT.

摘要翻译： 用于产品开发的测试卡系统包括被测设备（DUT）。 DUT包括：安装平面; 耦合到所述安装平面的电力输入端口; 耦合到安装平面的JTAG输入端口; 耦合到JTAG输入端口的时钟信号分配网络; 耦合到时钟信号分配网络和电力输入端口的多个锁存器; 以及耦合到所述多个锁存器的输出端口。 测试卡（TC）耦合到DUT，包括：耦合到DUT JTAG输入端口并被配置为向DUT提供测试数据的JTAG接口; 时钟模块，其耦合到所述DUT时钟信号分配网络并且被配置为生成时钟信号; 以及耦合到DUT输出端口并被配置为从DUT接收数据的分析模块。

公开(公告)号：US20080307282A1

公开(公告)日：2008-12-11

申请号：US11758708

申请日：2007-06-06

申请人： Richard Dono ,  Roger D. Weekly

发明人： Richard Dono ,  Roger D. Weekly

IPC分类号： G06F11/25

CPC分类号： G01R31/318533

摘要： A test card system for use in product development includes a device under test (DUT). The DUT comprises: a mount plane; a power input port coupled to the mount plane; a JTAG input port coupled to the mount plane; a clock signal distribution network coupled to the JTAG input port; a plurality of latches coupled to the clock signal distribution network and the power input port; and an output port coupled to the plurality of latches. A test card (TC) couples to the DUT, comprising: a JTAG interface coupled to the DUT JTAG input port and configured to provide test data to the DUT; a clock module coupled to the DUT clock signal distribution network and configured to generate a clock signal; and an analysis module coupled to the DUT output port and configured to receive data from the DUT.

摘要翻译： 用于产品开发的测试卡系统包括被测设备（DUT）。 DUT包括：安装平面; 耦合到所述安装平面的电力输入端口; 耦合到安装平面的JTAG输入端口; 耦合到JTAG输入端口的时钟信号分配网络; 耦合到时钟信号分配网络和电力输入端口的多个锁存器; 以及耦合到所述多个锁存器的输出端口。 测试卡（TC）耦合到DUT，包括：耦合到DUT JTAG输入端口并被配置为向DUT提供测试数据的JTAG接口; 时钟模块，其耦合到所述DUT时钟信号分配网络并且被配置为生成时钟信号; 以及耦合到DUT输出端口并被配置为从DUT接收数据的分析模块。