-
公开(公告)号：US08782478B2
公开(公告)日：2014-07-15
申请号：US14048362
申请日：2013-10-08
IPC分类号： G11C29/00
CPC分类号： G11C29/38 , G06F11/073 , G06F11/0754 , G11C16/3418
摘要： A non-volatile memory system includes a memory array and a memory controller. The memory controller is configured to perform a first array integrity read operation of the array until an error is detected. The controller is also configured to determine that the error is not error correction code (ECC) correctable. A first word line voltage associated with the error is characterized as being a first threshold voltage. The controller is further configured to perform a second array integrity read operation of the array. The second array integrity read operation includes reading the array with a word line read voltage that is offset from the first threshold voltage and is based on a predetermined width offset reference value. Finally, the controller is configured to check a check sum value resulting from the second array integrity read operation to determine when an imminent failure in the memory array is indicated.
摘要翻译： 非易失性存储器系统包括存储器阵列和存储器控制器。 存储器控制器被配置为执行阵列的第一阵列完整性读取操作，直到检测到错误。 控制器还被配置为确定错误不是纠错码（ECC）可校正。 与误差相关联的第一字线电压被表征为第一阈值电压。 控制器还被配置为执行阵列的第二阵列完整性读操作。 第二阵列完整性读操作包括使用偏离第一阈值电压的字线读取电压读取阵列，并且基于预定的宽度偏移参考值。 最后，控制器被配置为检查由第二阵列完整性读操作产生的校验和值，以确定何时指示存储器阵列中即将发生的故障。
-
公开(公告)号：US20140040687A1
公开(公告)日：2014-02-06
申请号：US14048362
申请日：2013-10-08
IPC分类号： G11C29/38
CPC分类号： G11C29/38 , G06F11/073 , G06F11/0754 , G11C16/3418
摘要： A non-volatile memory system includes a memory array and a memory controller. The memory controller is configured to perform a first array integrity read operation of the array until an error is detected. The controller is also configured to determine that the error is not error correction code (ECC) correctable. A first word line voltage associated with the error is characterized as being a first threshold voltage. The controller is further configured to perform a second array integrity read operation of the array. The second array integrity read operation includes reading the array with a word line read voltage that is offset from the first threshold voltage and is based on a predetermined width offset reference value. Finally, the controller is configured to check a check sum value resulting from the second array integrity read operation to determine when an imminent failure in the memory array is indicated.
摘要翻译： 非易失性存储器系统包括存储器阵列和存储器控制器。 存储器控制器被配置为执行阵列的第一阵列完整性读取操作，直到检测到错误。 控制器还被配置为确定错误不是纠错码（ECC）可校正。 与误差相关联的第一字线电压被表征为第一阈值电压。 控制器还被配置为执行阵列的第二阵列完整性读操作。 第二阵列完整性读操作包括使用偏离第一阈值电压的字线读取电压读取阵列，并且基于预定的宽度偏移参考值。 最后，控制器被配置为检查由第二阵列完整性读操作产生的校验和值，以确定何时指示存储器阵列中即将发生的故障。
-
搜索结果
2 条记录 (耗时 0.022 秒)
