公开(公告)号：US08467528B2

公开(公告)日：2013-06-18

申请号：US11847786

申请日：2007-08-30

申请人： Richard K. Sita ,  Kunal K. Dave ,  Jitesh Arora ,  Michael J. Erwin

发明人： Richard K. Sita ,  Kunal K. Dave ,  Jitesh Arora ,  Michael J. Erwin

IPC分类号： H04N7/167

CPC分类号： G06F21/10 ,  G06F21/575

摘要： A system on a chip including a bus, a bootup module coupled to the bus and configured to cause the system on a chip to bootup in accordance with a selected security mode, an input module coupled to the bus and configured to receive an input signal and to provide the input signal to the bus, a processor coupled to the bus and configured to process the input signal to provide an intermediate signal, in accordance with a type of content protection associated with the input signal, an encryption module coupled to the bus and configured to cause at least a portion of the intermediate signal to be encrypted to produce an encrypted signal, in accordance with the type of the content protection, and an output module coupled to the bus and configured to output the encrypted signal.

摘要翻译： 一种芯片上的系统，包括总线，启动模块，其耦合到所述总线并且被配置为使芯片上的系统根据所选择的安全模式引导;输入模块，耦合到所述总线并被配置为接收输入信号;以及 以向总线提供输入信号，处理器耦合到总线并被配置为根据与输入信号相关联的内容保护的类型来处理输入信号以提供中间信号，耦合到总线的加密模块和 被配置为使得所述中间信号的至少一部分被加密以根据所述内容保护的类型产生加密信号，以及耦合到所述总线并被配置为输出加密信号的输出模块。

公开(公告)号：US20080168266A1

公开(公告)日：2008-07-10

申请号：US11847786

申请日：2007-08-30

申请人： Richard K. Sita ,  Kunal K. Dave ,  Jitesh Arora ,  Michael J. Erwin

发明人： Richard K. Sita ,  Kunal K. Dave ,  Jitesh Arora ,  Michael J. Erwin

IPC分类号： G06F15/177 ,  H04L9/06

CPC分类号： G06F21/10 ,  G06F21/575

摘要： A system on a chip including a bus, a bootup module coupled to the bus and configured to cause the system on a chip to bootup in accordance with a selected security mode, an input module coupled to the bus and configured to receive an input signal and to provide the input signal to the bus, a processor coupled to the bus and configured to process the input signal to provide an intermediate signal, in accordance with a type of content protection associated with the input signal, an encryption module coupled to the bus and configured to cause at least a portion of the intermediate signal to be encrypted to produce an encrypted signal, in accordance with the type of the content protection, and an output module coupled to the bus and configured to output the encrypted signal.

摘要翻译： 一种芯片上的系统，包括总线，启动模块，其耦合到所述总线并且被配置为使芯片上的系统根据所选择的安全模式引导;输入模块，耦合到所述总线并被配置为接收输入信号;以及 以向总线提供输入信号，处理器耦合到总线并被配置为根据与输入信号相关联的内容保护的类型来处理输入信号以提供中间信号，耦合到总线的加密模块和 被配置为使得所述中间信号的至少一部分被加密以根据所述内容保护的类型产生加密信号，以及耦合到所述总线并被配置为输出加密信号的输出模块。

公开(公告)号：US08566382B2

公开(公告)日：2013-10-22

申请号：US12555122

申请日：2009-09-08

申请人： Larry Pearlstein ,  Richard K. Sita

发明人： Larry Pearlstein ,  Richard K. Sita

IPC分类号： G06F17/15 ,  G06F17/00

CPC分类号： G06F17/142 ,  G06F7/785 ,  G06F9/3001 ,  G06F9/30141 ,  G06F9/345 ,  G06F9/3824 ,  G06F9/3895

摘要： Apparatus and methods for storing data in a block to provide improved accessibility of the stored data in two or more dimensions. The data is loaded into memory macros constituting a row of the block such that sequential values in the data are loaded into sequential memory macros. The data loaded in the row is circularly shifted a predetermined number of columns relative to the preceding row. The circularly shifted row of data is stored, and the process is repeated until a predetermined number of rows of data are stored. A two dimensional (2D) data block is thereby formed. Each memory macro is a predetermined number of bits wide and each column is one memory macro wide.

摘要翻译： 用于将数据存储在块中以提供在两个或更多个维度中改进的存储数据的可访问性的装置和方法。 数据被加载到构成块的存储器宏中，使得数据中的顺序值被加载到顺序存储器宏中。 在行中加载的数据相对于前一行循环移位预定数量的列。 存储循环移位的数据行，重复该过程，直到存储预定数量的数据行。 由此形成二维（2D）数据块。 每个存储器宏是宽的预定位数，每列是一个宏存储器。

公开(公告)号：US20100077176A1

公开(公告)日：2010-03-25

申请号：US12555122

申请日：2009-09-08

申请人： Larry Pearlstein ,  Richard K. Sita

发明人： Larry Pearlstein ,  Richard K. Sita

IPC分类号： G06F12/00 ,  G06F12/02 ,  G06F15/76 ,  G06F9/02 ,  G06F9/302

CPC分类号： G06F17/142 ,  G06F7/785 ,  G06F9/3001 ,  G06F9/30141 ,  G06F9/345 ,  G06F9/3824 ,  G06F9/3895

摘要： Apparatus and methods for storing data in a block to provide improved accessibility of the stored data in two or more dimensions. The data is loaded into memory macros constituting a row of the block such that sequential values in the data are loaded into sequential memory macros. The data loaded in the row is circularly shifted a predetermined number of columns relative to the preceding row. The circularly shifted row of data is stored, and the process is repeated until a predetermined number of rows of data are stored. A two dimensional (2D) data block is thereby formed. Each memory macro is a predetermined number of bits wide and each column is one memory macro wide.

摘要翻译： 用于将数据存储在块中以提供在两个或更多个维度中改进的存储数据的可访问性的装置和方法。 数据被加载到构成块的存储器宏中，使得数据中的顺序值被加载到顺序存储器宏中。 在行中加载的数据相对于前一行循环移位预定数量的列。 存储循环移位的数据行，重复该过程，直到存储预定数量的数据行。 由此形成二维（2D）数据块。 每个存储器宏是宽的预定位数，每列是一个宏存储器。

公开(公告)号：US07016418B2

公开(公告)日：2006-03-21

申请号：US09923520

申请日：2001-08-07

申请人： Chun Wang ,  Paul Chow ,  Richard K. Sita ,  Philip L. Swan

发明人： Chun Wang ,  Paul Chow ,  Richard K. Sita ,  Philip L. Swan

IPC分类号： H04N7/12 ,  H04N9/64

CPC分类号： H04N21/4435 ,  H04N19/127 ,  H04N19/423 ,  H04N19/61

摘要： A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory. A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients.

公开(公告)号：US08225063B2

公开(公告)日：2012-07-17

申请号：US12457336

申请日：2009-06-08

申请人： Richard K. Sita

发明人： Richard K. Sita

IPC分类号： G06F12/00 ,  G06F1/04

CPC分类号： G06F13/1694

摘要： A memory interface allows access to SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates n (n>1) column memory addresses from the received column address. The interface accesses the synchronous dynamic memory to read or write n bursts of data at the n column memory addresses. Preferably, the SDRAM is clocked at n times the rate of the interconnected memory accessing device, and the memory units. The data units in the n bursts preferably have one nth the expected bit size. In this way, SDRAM may be accessed with high memory bandwidth, without requiring an increase in the size of data units in the SDRAM, and the associated data bus. Conveniently, the interface may be operable in two separate modes or configurations. In one mode, SDRAM may be accessed through the interface in a conventional manner. In the second mode, SDRAM is accessed in multiple bursts for each received burst access. The interface may form part of a memory accessing device, or may be a separate component for use with such a device.

摘要翻译： 存储器接口允许通过接收数据读取或写入数据单元的列地址来访问SDRAM。 突发中的每个数据单元具有预期的位大小。 接口从接收的列地址生成n（n> 1）列存储器地址。 该接口访问同步动态存储器以在n列存储器地址读取或写入数据的n个突发。 优选地，SDRAM以互连的存储器访问设备和存储器单元的速率的n倍计时。 n个突发中的数据单元优选地具有预期比特大小的第n个。 以这种方式，可以以高存储器带宽访问SDRAM，而不需要增加SDRAM中的数据单元的大小和相关联的数据总线。 方便地，接口可以以两种分开的模式或配置来操作。 在一种模式中，可以通过接口以常规方式访问SDRAM。 在第二模式中，对于每个接收到的突发存取，以多个突发存取SDRAM。 接口可以形成存储器访问设备的一部分，或者可以是用于与这样的设备一起使用的单独组件。

公开(公告)号：US07898547B2

公开(公告)日：2011-03-01

申请号：US11627585

申请日：2007-01-26

申请人： Chun Wang ,  Youjing Zhang ,  Richard K. Sita ,  Glen T. McDonnell ,  Babs L. Carter

发明人： Chun Wang ,  Youjing Zhang ,  Richard K. Sita ,  Glen T. McDonnell ,  Babs L. Carter

IPC分类号： G09G5/39 ,  G06F13/18 ,  G06F13/00

CPC分类号： G06F13/1663 ,  G09G5/39 ,  G09G2360/12 ,  G09G2360/122 ,  H04N19/423 ,  H04N19/439 ,  H04N19/44

摘要： A method and system is provided for organizing and routing multiple memory requests from a plurality of clients to multiple memories. Requests from a plurality of clients, including a plurality of clients of the same type, such as multiple MPEG decoders, are directed to different memory controllers by a router. The memory controllers order the client requests by requests among similar client types. The memory controllers also order the client requests by different client types. The ordered requests are then delivered to memory. Returned data is sent back to the clients. A method of mapping motion pictures experts group (MPEG) video information for improved efficiency is presented, wherein image information is stored in blocks of memory referred to as tiles. Tiles are mapped in memory so that adjacent tiles only correspond to different banks of memory.

摘要翻译： 提供了一种方法和系统，用于组织和将多个存储器请求从多个客户端路由到多个存储器。 来自包括多个相同类型的多个客户端（诸如多个MPEG解码器）的多个客户端的请求被路由器定向到不同的存储器控​​制器。 内存控制器通过类似客户端类型的请求命令客户端请求。 内存控制器还可以通过不同的客户端类型对客户端请求进行排序。 然后将有序请求传递到内存。 返回的数据将发送回客户端。 提出了一种映射运动图像专家组（MPEG）视频信息以提高效率的方法，其中将图像信息存储在被称为瓦片的存储器块中。 瓷砖被映射到存储器中，使得相邻的瓦片仅对应于不同的存储器组。

公开(公告)号：US20090316041A1

公开(公告)日：2009-12-24

申请号：US12144018

申请日：2008-06-23

申请人： Larry Pearlstein ,  Richard K. Sita

发明人： Larry Pearlstein ,  Richard K. Sita

IPC分类号： H04N5/917

CPC分类号： H04N5/91 ,  H04N5/765 ,  H04N19/184

摘要： A method and apparatus of processing image data comprises receiving a video data signal where each pixel is represented by one or more digitized components, each digitized component being represented by a first set of binary digits and a second set of binary digits. The first set of binary digits is stored in a first memory plane and the second set of binary digits is stored in a second memory plane. The first set of binary digits is extracted and undergoes first and second processing. The second set of binary digits is extracted and undergoes second processing.

摘要翻译： 处理图像数据的方法和装置包括：接收视频数据信号，其中每个像素由一个或多个数字化分量表示，每个数字化分量由第二组二进制数字和第二组二进制数字表示。 第一组二进制数字存储在第一存储器平面中，第二组二进制数字被存储在第二存储器平面中。 提取第一组二进制数字并进行第一和第二处理。 提取第二组二进制数字并进行第二次处理。

公开(公告)号：US08306122B2

公开(公告)日：2012-11-06

申请号：US12144018

申请日：2008-06-23

申请人： Larry Pearlstein ,  Richard K. Sita

发明人： Larry Pearlstein ,  Richard K. Sita

IPC分类号： H04N7/12 ,  H04N11/02 ,  H04N11/04

CPC分类号： H04N5/91 ,  H04N5/765 ,  H04N19/184

摘要： A method and apparatus of processing image data comprises receiving a video data signal where each pixel is represented by one or more digitized components, each digitized component being represented by a first set of binary digits and a second set of binary digits. The first set of binary digits is stored in a first memory plane and the second set of binary digits is stored in a second memory plane. The first set of binary digits is extracted and undergoes first and second processing. The second set of binary digits is extracted and undergoes second processing.

摘要翻译： 处理图像数据的方法和装置包括：接收视频数据信号，其中每个像素由一个或多个数字化分量表示，每个数字化分量由第二组二进制数字和第二组二进制数字表示。 第一组二进制数字存储在第一存储器平面中，第二组二进制数字被存储在第二存储器平面中。 提取第一组二进制数字并进行第一和第二处理。 提取第二组二进制数字并进行第二次处理。

公开(公告)号：US20090254699A1

公开(公告)日：2009-10-08

申请号：US12457336

申请日：2009-06-08

申请人： Richard K. Sita

发明人： Richard K. Sita

IPC分类号： G06F12/00 ,  G06F1/04

CPC分类号： G06F13/1694

摘要： A memory interface allows access to SDRAM by receiving a column address for a data read or write of a burst of data units. Each data unit in the burst has an expected bit size. The interface generates n (n>1) column memory addresses from the received column address. The interface accesses the synchronous dynamic memory to read or write n bursts of data at the n column memory addresses. Preferably, the SDRAM is clocked at n times the rate of the interconnected memory accessing device, and the memory units. The data units in the n bursts preferably have one nth the expected bit size. In this way, SDRAM may be accessed with high memory bandwidth, without requiring an increase in the size of data units in the SDRAM, and the associated data bus. Conveniently, the interface may be operable in two separate modes or configurations. In one mode, SDRAM may be accessed through the interface in a conventional manner. In the second mode, SDRAM is accessed in multiple bursts for each received burst access. The interface may form part of a memory accessing device, or may be a separate component for use with such a device.

摘要翻译： 存储器接口允许通过接收数据读取或写入数据单元的列地址来访问SDRAM。 突发中的每个数据单元具有预期的位大小。 接口从接收的列地址生成n（n> 1）列存储器地址。 该接口访问同步动态存储器以在n列存储器地址读取或写入数据的n个突发。 优选地，SDRAM以互连的存储器访问设备和存储器单元的速率的n倍计时。 n个突发中的数据单元优选地具有预期比特大小的第n个。 以这种方式，可以以高存储器带宽访问SDRAM，而不需要增加SDRAM中的数据单元的大小和相关联的数据总线。 方便地，接口可以以两种分开的模式或配置来操作。 在一种模式中，可以通过接口以常规方式访问SDRAM。 在第二模式中，对于每个接收到的突发存取，以多个突发存取SDRAM。 接口可以形成存储器访问设备的一部分，或者可以是用于与这样的设备一起使用的单独组件。