公开(公告)号：US4583168A

公开(公告)日：1986-04-15

申请号：US530996

申请日：1983-09-12

申请人： Richard Pang ,  Hemraj K. Hingarh

发明人： Richard Pang ,  Hemraj K. Hingarh

IPC分类号： G06F15/78 ,  G06F12/00

CPC分类号： G06F15/7832

摘要： A microprocessor integrated circuit (50) has a read only memory (ROM) (400) which is X and Y addressible and is word, bit and page oriented. The microprocessor integrated circuit (50) has a main injector bus (602) and a ground return bus (604) with a branch ground bus (608) connected to the ground return bus (604) through a ground-balancing resistor (610) in a data path. The circuit (50) has a register file (82) with registers (622) connected to a local bus (604). The local busses (604) are connected to a main bus (602) through a multiplexer (605). The microprocessor integrated circuit (50) includes a D-type flip-flop circuit (700) with asynchronous clear and preset. A latch dual port random access memory (RAM) circuit (900) is employed in the register file (82) of the microprocessor integrated circuit (50).

摘要翻译： 微处理器集成电路（50）具有只读存储器（ROM）（400），其是X和Y可寻址的，并且是字，位和页面定向的。 微处理器集成电路（50）具有主注射器总线（602）和接地返回总线（604），其中分支接地总线（608）通过接地平衡电阻（610）连接到接地返回总线（604） 数据路径。 电路（50）具有寄存器文件（82），其寄存器（622）连接到本地总线（604）。 本地总线（604）通过多路复用器（605）连接到主总线（602）。 微处理器集成电路（50）包括具有异步清除和预设的D型触发器电路（700）。 在微处理器集成电路（50）的寄存器文件（82）中采用锁存双端口随机存取存储器（RAM）电路（900）。

公开(公告)号：US20070171756A1

公开(公告)日：2007-07-26

申请号：US11301401

申请日：2005-12-13

申请人： Emil Lambrache ,  Duncan Curry ,  Richard Pang

发明人： Emil Lambrache ,  Duncan Curry ,  Richard Pang

IPC分类号： G11C8/00

CPC分类号： G11C16/0433 ,  G11C16/3418 ,  G11C16/3427

摘要： A byte select circuit of a memory cell array wherein each column of the memory cell array has two byte select lines. A first byte select line is coupled to the even numbered rows in the column and a second byte select line is coupled to the odd numbered rows in the column. The second byte select line is configured to be driven to a low voltage level when the first byte select line is driven to a high voltage level, thereby minimizing or eliminating any parasitic voltage coupling between adjacent rows of memory cells.

公开(公告)号：US20070140002A1

公开(公告)日：2007-06-21

申请号：US11303368

申请日：2005-12-16

申请人： Emil Lambrache ,  Duncan Curry ,  Richard Pang

发明人： Emil Lambrache ,  Duncan Curry ,  Richard Pang

IPC分类号： G11C16/04 ,  G11C11/34 ,  G11C16/06

CPC分类号： G11C16/3418 ,  G11C16/3427

摘要： A memory array and method for performing a write operation in a memory array that eliminates parasitic coupling between selected and unselected bitlines and protects memory cells on unselected bitlines. A memory array has a plurality of memory cells, each of which is coupled to a unique array bitline. A unique recovery transistor is coupled to each array bitline. The recovery transistors on odd bitlines are coupled to a first and second voltage, while the recovery transistors on even bitlines are coupled to a first and third voltage. During a write operation, each recovery transistor coupled to an unselected bitline is active during a write operation and a recovery operation, while each recovery transistor coupled to a selected bitline is active during a recovery operation. The first voltage is sufficient to prevent parasitic coupling between the selected bitlines and the unselected bitlines during the write operation.